Z86U18 Datasheet, PDF (16/30 Pages) Zilog, Inc. – USB Device Controller with CMOS Z86K15 MCU

Z86U18
USB Device Controller with CMOS Z86K15 MCU
FUNCTIONAL DESCRIPTION (Continued)
Watch-Dog Timer. The Watch-Dog Timer is activated au-
tomatically by power-on
WDT Hot bit. Bit 7 of the Interrupt Request register (IRQ
register FAH) determines whether a hot start or cold start
occurred. A cold start is defined as reset occurring from
the power-up of the Z86U18 (the default upon power-up is
0). A hot start occurs when a WDT time-out has occurred
(bit 7 is set to 1). Bit 7 of the IRQ register is read-only and
is automatically reset to 0 when accessed.
Zilog
Watch-Dog Timer Mode Register (WDTMR). The WDT-
MR is: WDT (ms) » 50 ms.
WDT During HALT (D5-R250). This bit determines wheth-
er or not the WDT is active during HALT Mode. The default
is 1, and a 1 indicates active during HALT.
VCC
Internal
Reset
18 Tpc
POR
* Reset Delay = POR 98.57 ms at 6 MHz.
Reset
Delay
Figure 16. WDT Turn-On Timing After Reset
16
PRELIMINARY
DS97KEY0102