Z86U18 Datasheet, PDF (22/30 Pages) Zilog, Inc. – USB Device Controller with CMOS Z86K15 MCU

Z86U18
USB Device Controller with CMOS Z86K15 MCU
REGISTER DESCRIPTIONS (Continued)
Zilog
001h
D7 D6 D5 D4 D3 D2 D1 D0
Out _pkt _rdy
In _pkt _rdy
Force Stall
Data End
Setup End
Send Stall
Serviced Out Packet Ready
Serviced Setup End
Bit No
7
6
5
Bit Description
Serviced Setup End
Serviced Outpacket
Ready
Send STALL
4
Setup End
3
Data End
2
Force STALL
1
In Packet Ready
0
Out Packet Ready
Figure 31. Endpoint 0 CS Register
mC SIE Description
W R The microcontroller writes a 1 to this register to clear setup end bit.
W R The microcontroller writes a 1 to this register to clear out packet ready
bit.
W R If the microcontroller decodes an invalid descriptor, it writes a 1 to this
register before clearing out_pkt_rdy bit or when microcontroller decodes
a set feature or clear feature USB command from the host.
R W If the function receives a new setup transaction before the previous one
is complete (entire length of data is transferred), this bit is set. Upon
seeing this bit set, the microcontroller should abort the current set
operation.
W R During the data phase of a control transfer after the microcontroller has
received/sent the last data as speciÞed in the setup phase, it sets this
bit.
R W The SIE writes to this register, when it encounters a protocol violation,
and issues a STALL handshake to the current control transfer.
W R During the data phase, after the microcontroller has Þlled the data, it sets
this bit. It is cleared by SIE upon successful transmittion of data.
R W The SIE sets this bit after writing data to the FIFO. The microcontroller
clears this bit by writing it to Serviced Out Packet Ready bit.
002h
D7 D6 D5 D4 D3 D2 D1 D0
Write Count
00000
Figure 32. Endpoint 0 Write Count Register
Bit
mC
SIE
Description
2:0
R
W
The contents indicates the number of bytes in the FIFO.
22
PRELIMINARY
DS97KEY0102