Z86U18 Datasheet, PDF (17/30 Pages) Zilog, Inc. – USB Device Controller with CMOS Z86K15 MCU

Zilog
Z86U18
USB Device Controller with CMOS Z86K15 MCU
Interrupts. The Z86U18 has five different interrupts from To accommodate polled interrupt systems, interrupt inputs
three different groups. These interrupts are maskable and are masked and the interrupt request register is polled to
prioritized (Figure 17). The five sources are divided as fol- determine which of the interrupt request needs service.
lows: three sources are claimed by Port 3 lines P33-P31,
1
one is claimed by the counter/timer, and the other is ^{EMI. Lower EMI on the Z86U18 is achieved through circuit}
claimed by the USB interface. The Interrupt Masked Reg- ^{modifications. The internal divide-by-two circuit has been}
ister globally or individually enables or disables the six in- ^{removed to further reduce EMI.}
terrupts requests.
The Z86U18 also accepts external clock from Pin 33 (40-
Pin DIP).
IRQ0-IRQ4
5
IRQ
XTAL1 (in)
IMR
5
IPR
Global
Interrupt
Enable
Priority
Logic
Vector Select
Figure 17. Interrupt Block Diagram
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder that is con-
trolled by the Interrupt Priority register. All interrupts are
vectored through locations in the program memory. When
an interrupt machine cycle is activated an interrupt request
is granted. Thus, this disables all of the subsequent inter-
rupts, saves the Program Counter and status flags, and
then branches to the program memory vector location re-
served for that interrupt. This memory location and the
next byte contain the 16-bit address of the interrupt service
routine for that particular interrupt request.
XTAL2 (out)
XTAL1
External Clock
Figure 18. Oscillator ConÞguration
DS97KEY0102
PRELIMINARY
17