MT90528 Datasheet, PDF (98/195 Pages) Zarlink Semiconductor Inc – 28-Port Primary Rate Circuit Emulation AAL1 SAR

MT90528
Data Sheet
TDM Bus
Module
STiCLK0
STiCLK1
STiCLK27
MT90528
Clock Management Module
{(PRI_SEL[5]|PRI_LOS),PRI_SEL<4:0>}
PLLCLK0
PLLCLK1
PLLCLK27
.
.
. _56:2
Mux
.
.
.
PRI_REF
Clock Rates:
DS1 = 1.544 MHz
E1 = 2.048 MHz (also used for
framed DS1)
ST-BUS = 4.096 MHz
External PLL
(e.g., MT9042)
.
.
.
56:2
Mux
.
.
.
SEC_REF
SEC_SEL<5:0>
TDM_CLK
(Synchronous Clock #2)
TDM_CLK
Figure 37 - Synchronous TDM Rate Clock Generated by External PLL User-Selectable
References
4.7.2.3 Network Clock Divider Circuit
This sub-module is implemented only once within the MT90528 device and is used by both the Transmit SRTS and
Receive SRTS processes. The required circuitry is shown in Figure 38.
The primary function of this sub-module is to create a divided-down network clock, fnxi, from a PHY rate clock
(19.44 MHz) which is obtained from an external pin. This sub-module generates a number of different clock rates in
accordance with the requirements of the SRTS patent and the CES specification.
When operating in UDT mode, only a single multiplexer is required for RTS generation and SRTS clock recovery.
Since all of the VCs contain the same amount of data, only one network clock rate is required. This rate is set out in
the CES specification, af-vtoa-0078.000, as 2.430 MHz.
In SDT mode, additional network clock rates are required because the size of the transmitted VCs can differ. The
MT90528 permits RTS generation and SRTS clock recovery to be conducted on two different VC sizes (ranging
from n = 1 to n = 32) for each device configuration.
98
Zarlink Semiconductor Inc.