MT90528 Datasheet, PDF (167/195 Pages) Zarlink Semiconductor Inc – 28-Port Primary Rate Circuit Emulation AAL1 SAR

MT90528
Data Sheet
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
Address Setup - (R/W, AEM and t_ADDS
0
ns
CPU_ADD[20:1] VALID) to (CS and DS
asserted)
Address Hold - (CS or DS de-asserted) to t_ADDH
0
ns
(AEM, CPU_ADD[20:1] and R/W INVALID)
DTACK High - CS asserted to DTACK t_RDTKH
0
driven high
10
ns C_L = 75 pF
DTACK Delay - (CS and DS asserted) to
DTACK asserted
t_RACC
Register access
197
228
Memory access
213
DTACK High-Impedance - CS de- t_RDTKZ
0
asserted to DTACK high-impedance
243
2021
10
ns C_L = 75 pF
13 MCLK < t_RACC < 16 MCLK
14 MCLK < t_RACC < 133 MCLK
ns C_L = 75 pF
Data Output Setup - CPU_DATA[15:0]
t_DS
16
VALID to DTACK asserted
ns C_L = 75 pF
~ 1 MCLK cycle
Data Output Hold - (CS or DS de-
t_DH
0
asserted) to CPU_DATA[15:0] INVALID
ns C_L = 75 pF
Note 1: MCLK = 66 MHz (15.2 ns)
Note 2: Both CS and DS must be asserted for a read cycle to occur. A read cycle is completed when either CS or DS is de-asserted.
Note 3: There should be a minimum of 3 MCLK periods between CPU accesses, to allow the MT90528 to recognize the accesses as
separate (i.e., CS must be de-asserted for 3 MCLK cycles between CPU accesses).
Table 93 - Motorola Microprocessor Interface Timing - Read Cycle Parameters
t_RACC
CS
V_TT
DS
t_RDTKH
DTACK
t_ADDS
CPU_ADD[20:1]
AEM
R_W
CPU_DATA[15:0]
ADDRESS VALID
t_ADDH
t_RDTKZ
t_ADDH
t_DS
t_DH
DATA VALID
V_TT
V_TT
V_TT
V_TT
V_TT
Figure 49 - Motorola CPU Interface Timing - Read Access
167
Zarlink Semiconductor Inc.