MT90528 Datasheet, PDF (181/195 Pages) Zarlink Semiconductor Inc – 28-Port Primary Rate Circuit Emulation AAL1 SAR

MT90528
Data Sheet
UTO_IN_CLK
t_UTX2P
UTO_IN_ADDR[4:0]
M
See Note 1
t_UTXD
UTO_IN_ENBATM
_CLAVPHY
t_UTXZX
UTO_IN_CLAVAT
M_ENBPHY
UTO_IN_DATA[15:0]
See Note 2
UTO_IN_SOC
t_UTX2H t_UTX2L
t_UTXIS
t_UTXIH
1F N 1F M 1F N 1F N
t_UTXDZ
t_UTXH
t_UTXIS
t_UTXIH
X
H1 H2 H3 P1
t_UTXIS
t_UTXIH
V_TT
N _1F N
V_TT
t_UTXIS
V_TT
t_UTXIH
V_TT
P23 P24
X V_TT
V_TT
Note 1: M is the address of the MT90528; N is the address of another PHY device, where N is not equal to M. An
address of 1Fh (31d) indicates a null PHY port.
Note 2: UTO_IN_DATA is a 16-bit bus; therefore, P24 indicates the last cell payload word to be transmitted.
Figure 65 - UTOPIA Level 2 Interface Timing - PHY Mode - Incoming Data (UTOPIA TX Bus)
Characteristic
Sym. Min.
Ty.p Max. Units
Test Conditions
UTO_OUT_CLK Period
UTO_OUT_CLK Pulse Width (HIGH / LOW)
Input Setup Time -
(UTO_OUT_CLAVATM_ENBPHY asserted
and UTO_OUT_ADDR[4:0] VALID) to
UTO_OUT_CLK rising
Input Hold Time - UTO_IN_CLK rising to
(UTO_OUT_ADDR[4:0] INVALID and
UTO_OUT_CLAVATM_ENBPHY de-asserted)
t_URX2P
t_URX2H/L
t_URXIS
t_URXIH
19.23
7.7
4
1
t_URX2P/2
ns UTO_OUT_CLK = 52 MHz
ns
ns
ns
Output Delay - UTO_OUT_CLK rising to
(UTO_OUT_ENBATM_CLAVPHY,
UTO_OUT_SOC asserted and
UTO_OUT_DATA[15:0] VALID)
t_URXD
Output Hold Time - UTO_OUT_CLK rising to t_URXH
1
(UTO_OUT_DATA[15:0] INVALID and
1
UTO_OUT_ENBATM_CLAVPHY,
UTO_OUT_SOC de-asserted)
13.5
20.5
ns C_L = 40 pF; UTO_OUT_CLK < 52 MHz
ns C_L = 80 pF; UTO_OUT_CLK < 33 MHz
ns C_L = 40 pF; UTO_OUT_CLK < 52 MHz
ns C_L = 80 pF; UTO_OUT_CLK < 33 MHz
Drive to High-Z - UTO_OUT_CLK rising to
(UTO_OUT_ENBATM_CLAVPHY,
UTO_OUT_SOC, UTO_OUT_DATA[15:0]
HIGH-Z)
t_URXDZ
1
1
17.5
28.5
ns C_L = 40 pF; UTO_OUT_CLK < 52 MHz
ns C_L = 80 pF; UTO_OUT_CLK < 33 MHz
Table 106 - UTOPIA Level 2 Interface Timing - PHY mode - Outgoing Data (UTOPIA RX Bus)
181
Zarlink Semiconductor Inc.