MT90528 Datasheet, PDF (75/195 Pages) Zarlink Semiconductor Inc – 28-Port Primary Rate Circuit Emulation AAL1 SAR

MT90528
Data Sheet
Current State
Transition Event
Action Taken
Next State
sync
late cell timeout period reached and
CHECK_LATE_ARRIVALS = ‘1’
- UDT RX_SAR inserts a single
dummy cell
late_cell_insertion
invalid sequence number
- accept received cell
invalid
received cell is in sequence with previous cell
- accept received cell
- per-port timeout circuitry is
enabled to permit late-cell
insertions
sync
received cell is not in sequence with the
previously-received cell -> received cell has a
sequence number one greater than the
expected sequence number
- assume single-cell loss event
- UDT RX_SAR inserts a single
dummy cell
- after dummy cell insertion, accept
received cell (in-order dummy cell
insertion)
- declare aal1_seq_error
single_cell_loss_
misinsertion
received cell is not in sequence with the
previously-received cell -> received cell has a
sequence number that is NOT one greater
than the expected sequence number
- cannot assume what happened
(may be a multi-cell loss case)
- accept received cell (thus, if this is
a multi-cell loss case, out-of-order
dummy cell insertion will occur)
- declare aal1_seq_error
out_of_seq
invalid
invalid sequence number
- discard cell
start
received cell is in sequence with last “good”
cell (i.e., cell misinsertion)
- discard cell
- declare misinserted_cell_error
- per-port timeout circuitry is
enabled to permit late-cell
insertions
sync
received cell has a valid sequence number
that is two greater than the last “good” cell
(i.e., sequence number protection failure)
- accept received cell
- per-port timeout circuitry is
enabled to permit late-cell
insertions
sync
received cell has valid sequence number, but - discard cell
doesn’t meet either of the 2 previous criteria
out_of_sync
out_of_seq
invalid sequence number
- discard cell
start
received cell is in sequence with last received
cell (i.e., multiple cell loss)
- calculate number of lost cells (up
to 7)
- UDT RX_SAR inserts dummy
cell(s)
- after dummy cell insertion(s),
accept received cell
- declare lost_cell_error
- per-port timeout circuitry is
enabled to permit late-cell
insertions
sync
received cell has a valid sequence number
that is two greater than the last in-sequence
cell (i.e., sequence number protection failure)
- accept received cell
- per-port timeout circuitry is
enabled to permit late-cell
insertions
sync
received cell has valid sequence number, but - discard cell
doesn’t meet either of the 2 previous criteria
out_of_sync
Table 15 - Operation of UDT Fast Sequence Number Processing State Machine
Note
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Zarlink Semiconductor Inc.