MT90528 Datasheet, PDF (11/195 Pages) Zarlink Semiconductor Inc – 28-Port Primary Rate Circuit Emulation AAL1 SAR

MT90528
Data Sheet
List of Figures
Figure 49 - Motorola CPU Interface Timing - Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 50 - Motorola CPU Interface Timing - Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 51 - External Memory Interface Timing - Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 52 - External Memory Interface Timing - Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 53 - Nominal UDT Mode Timing Diagram - DS1 (1.544 Mbps) and E1 (2.048 Mbps) . . . . . . . . . . . . . . . 171
Figure 54 - Nominal SDT Mode Timing Diagram - Generic and ST-BUS DS1 or E1 (2.048 Mbps). . . . . . . . . . . 171
Figure 55 - Nominal SDT Mode Timing Diagram - Generic DS1 (1.544 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 56 - TDM Bus Inputs - Generic Bus Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 57 - TDM Bus Inputs - ST-BUS Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 58 - TDM Bus Output Clocking Parameters - Generic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 59 - TDM Bus Output Clocking Parameters - ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 60 - TDM Bus Outputs - Serial Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 61 - UTOPIA Level 1 Interface Timing - ATM Mode - Incoming Data (UTOPIA RX Bus) . . . . . . . . . . . . . 176
Figure 62 - UTOPIA Level 1 Interface Timing - ATM Mode - Outgoing Data (UTOPIA TX Bus) . . . . . . . . . . . . . 177
Figure 63 - UTOPIA Level 1 Interface Timing - PHY Mode - Incoming Data (UTOPIA TX Bus) . . . . . . . . . . . . . 178
Figure 64 - UTOPIA Level 1 Interface Timing - PHY Mode - Outgoing Data (UTOPIA RX Bus) . . . . . . . . . . . . . 179
Figure 65 - UTOPIA Level 2 Interface Timing - PHY Mode - Incoming Data (UTOPIA TX Bus) . . . . . . . . . . . . . 181
Figure 66 - UTOPIA Level 2 Interface Timing - PHY Mode - Outgoing Data (UTOPIA RX Bus) . . . . . . . . . . . . . 182
Figure 67 - External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 68 - ATM Mode: External UTOPIA Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 69 - PHY Mode: External UTOPIA Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
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