MT90528 Datasheet, PDF (39/195 Pages) Zarlink Semiconductor Inc – 28-Port Primary Rate Circuit Emulation AAL1 SAR

MT90528
Data Sheet
address is sampled by the memory. A flow-through write cycle requires that valid data be placed on the data bus
before the next rising clock edge after the address is sampled. On the other hand, data must be valid before the
second rising edge of the clock after the address is presented to memory in the case of pipelined RAM.
CLOCK
ADDRESS
DATA
ADDRESS1
ADDRESS2
DATA1
DATA1
Note: The number of clock cycles between an address (ADDRESS1) and its read data (DATA1) is
set according to the MTYP field in the Memory Arbiter Configuration Register at byte address
7000h.
Figure 8 - Memory Read Pipeline Length
CLOCK
ADDRESS
DATA
ADDRESS1
ADDRESS2
DATA1
DATA1
Note: The number of clock cycles between an address (ADDRESS1) and its written data
(DATA1) is set according to the MTYP field in the Memory Arbiter Configuration Register at byte
address 7000h.
Figure 9 - Memory Write Pipeline Length
Accesses to/from the external memory are made on a word-wide (i.e., 16-bit) basis. 2 optional bits,
MEM_DATA[17:16], can provide parity data regarding the external memory data. The external memory interface
module of the MT90528 generates MEM_DATA[17] to represent the even parity bit over MEM_DATA[15:8].
Similarly, MEM_DATA[16] represents the even parity bit over MEM_DATA[7:0]. When data is read from external
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Zarlink Semiconductor Inc.