MT90528 Datasheet, PDF (49/195 Pages) Zarlink Semiconductor Inc – 28-Port Primary Rate Circuit Emulation AAL1 SAR

MT90528
Data Sheet
The MT90528’s UTOPIA interface addresses reference configuration A of Figure 14 when it is operating in ATM
mode. This means that the interface communicates with one, and only one, PHY. When the UTOPIA module is
operating in PHY mode, it addresses reference configuration B of Figure 14.
The UTOPIA module does not address multi-PHY (MPHY) operation in ATM mode, nor does it address the use of
multiple CLAV signals.
A - 1 ATM and 1 PHY
MT90528
ATM
B - 1 ATM and multiple PHYs
PHY
MT90528
PHY1
(optional)
...
PHY N
(optional)
Figure 14 - UTOPIA Reference Configurations
The UTOPIA interface allows the user to choose between an 8-bit or 16-bit interface. The 8-bit interface is only
specified to a maximum UTOPIA clock-rate of 33 MHz (in the UTOPIA Level 2 specification); however, the
MT90528 interface is capable of operating up to 52 MHz.
The user can choose to have the UTOPIA interface emulate a PHY device or an ATM device. When the MT90528
is operating in PHY mode, it is capable of being polled; this allows the ATM device accessing the MT90528 to
operate in multi-PHY mode.
The UTOPIA interface contains a loopback configuration, where data received on the incoming port can be looped
back to the outgoing port. This is implemented to assist developers with debug and diagnostics.
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Zarlink Semiconductor Inc.