MV1403 Datasheet, PDF (9/18 Pages) Advanced Semiconductor – TUNING VARACTOR

MV1403
62.5µs
CLK 1
128
FRS
7.8125µs
15.625µs
144
176
208
240
D
D1 D2 D3 D4 D5 D6 D7 D8
Q
D1
D2
D3
D4
Figure 9: Timeslot sixteen receiver timing
RECEIVE DEMONSTRATION MODE, RX2
In the last mode (MODE = 1, DEMO = 1) the four receiver
macrocells are connected together internally to demonstrate
how they may be utilised to perform the required functions of a
2.048 MBit PCM receiver. The functional diagram of the
MV1403 will now be as shown in Fig. 11.
The received pseudo-ternary HDB3 data is input to the
HDB3 Decoder macrocell, which decodes this data and
outputs it to the other three macrocells and external circuitry,
as well as raising appropriate alarms as previously described
for the individual receive mode.
The Timeslot Zero Receiver then synchronises itself to the
Frame Alignment Signal present in this data stream and
produces various timing outputs tor use by the remaining two
receiver macrocells and external circuitry. In addition this
macrocell also raises appropriate alarms as required.
The data being output by the HDB3 decoder is used as the
D input to the Timeslot 16 Receiver macrocell which also uses
the Timeslot Zero Receiver’s TSZ output as its FRS timing
input. From this the macrocell determines the position of
timeslot 16 and extracts the 8 bits of signalling
data from this timeslot. This data is then converted into a
continuous 64kbit output data stream.
The Cyclic Redundancy Checker macrocell uses the HDB3
Decoder’s output data and the Timeslot Zero Receivers timing
outputs TSZ and TZS as its D, FRS and TZS inputs
respectively. From this information the macrocell synchronises
itself to the CRC multiframe alignment signal and performs its
CRC check procedure on the incoming data. Its two timing
outputs, FRS13 and FRS15, are input to the Timeslot Zero
Receiver to allow it to extract the international spare bits of the
CRC multiframe.
In non CRC mode, the Cyclic Redundancy Checker’s error
outputs are disabled by the alarm gating circuitry. When in
CRC mode, this circuitry will also disable the ER1 and ER2
alarms whilst the macrocell is out of multiframe alignment.
In addition to the required outputs, all the internal timing
signals are also available as outputs from the MV1403,
allowing the interaction of the macrocells to be observed.
MFD4 MFD3 MFQ3
LIA
MFQ4
DV
LIA
CDR
VDD
RXD1
HDB3DC
RXD2
Q
STM
MODE
DEMO
STM
MODE
DEMO
MODE
CLK
CONTROL
CLK ^CLK
Q1S, DQ1,
TZSRZ RST CRC DQ3-DQ8
M
(CRC)
Q1S, DQ1,
DQ3-DQ8
RST
TZS
FRS13
FRS15
RXTSZ
D TSZ
MFQ8
MSA
MSA
MFQ7
ER1 ALARM
GATING
ER1
CRCCHK
FRS
MFQ6
ER2
ER2
TZS
MFDS
VDD GND
FRS13
FRS15
D FRS
RXTS16
Q
FRS13 FRS15
MFQ9
RAI
ER
SA
CK8
CCR
PCM OUT
MFQ2
ER
MFQ1
CK8
CCR
MFQ5
TSZ
TSZRZ
Figure 11: RX2 receive demonstration mode functional diagram
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