MV1403 Datasheet, PDF (13/18 Pages) Advanced Semiconductor – TUNING VARACTOR

MV1403
PIN DESCRIPTIONS (continued)
Symbol Pin No.
Mode
name
DP48 HP44 (see note 1)
GND2 25
GLOBAL
DEMO 26
24
GLOBAL
MODE 27
25
GLOBAL
CLK
28
26
GLOBAL
STM 29
27
GLOBAL
P
30
28
GLOBAL
CRC 31
29
GLOBAL
MFD5 32
30
RX1
RX2
TX1
TX2
FRS 33
31
RX1
RX2
TX
TZS
34
32
RX1
RX2
TX1
.
MFD6 35
33
RX1
RX2
TX
GND3 36
GLOBAL
Pin name and description
Digital ground. 0V (Note 2)
Demonstration pin. A logic high on this pin puts the MV1403 into
demonstration mode, RX2 or TX2 with all the transmit or receive macrocells
connected together internally. A low on this pin allows access to the
macrocells individually (ie. RX1 or TX1 mode).
Transmit/Receive Mode pin. A logic high on this pin places the MV1403 in
Receive mode RX1 or RX2. A low places it in Transmit mode TX1 or TX2
2.048MHz Master Clock input.
Scan Path Test Mode pin. A logic high on this pin places the MV1403 in scan
test mode. For normal operation this pin should be tied low.
Scan Test Data input. In Scan Path Test Mode, this pin is used as the input to
the scan path.
CRC Mode pin. This pin is used as the CRC mode input to the CRCGEN (EN
input) or RXTSZ (M input) macrocells. A logic high on this pin will put the
MV1403 into Cyclic Redundancy Check mode.
Cyclic Redundancy Checker (CRCCHK) Macrocell - Data Input (D). This pin is
used as the 2.048Mbit serial data input to this macrocell.
This pin is unused since the D input ol the CRC Checker is connected
internally to the a output of the HDB3 Decoder.
Cyclic Redundancy Check Generator (CRCGEN) Macrocell - Data Input (D).
This pin is the 2.048 Mbit data input to this macrocell.
This pin is unused since the D input to the CRC Generator is connected
internally to the a output of the Transmission Multiplexer
Frame Sync Input (FRS). This pin is the 8kHz timeslot zero frame marker input
to the Timeslot Sixteen Receiver (RXTS16) and Cyclic Redundancy Checker
(CRCCHK) macrocells. It is required to be high only during timeslot zero of
each frame.
This pin is unused since the FRS inputs to the CRC Checker and Timeslot 16
Receiver are connected internally to the TSZ output of the Timeslot Zero
Receiver .
Frame Sync Input (FRS). This pin is the 8kHz timeslot zero frame marker
input. It is required to be high only during timeslot zero of each frame.
Cyclic Redundancy Checker (CRCCHK) Macrocell - Timeslot Zero Sync
Frame Marker Input (TZS). This 4KHz input is required to be high during
timeslot zero of sync frames and change at the beginning of bit 2, timeslot 1
of every frame.
This pin is unused since the TZS input of the CRC Checker is connected
internally to the TZS output of the Timeslot Zero Receiver.
Cyclic Redundancy Check Generator (CRCGEN) Macrocell Timeslot Zero
Sync Frame Marker Input (TZS). This 4kHz input is required to be high during
timeslot zero of sync frames and change at the beginning of bit 2, timeslot 1
of every frame.
Timeslot Sixteen Receiver (RXTS16) Macrocell - 2.048Mbit Serial Data Input
(D). The 8 bits of signalling data in timeslot t6 are extracted from this input
during timeslot 16.
This pin is unused since the D input of the Timeslot 16 Receiver is connected
intermally to the (; output of the HDB3 Decoder.
Timeslot Sixteen Transmitter (TXTS16) Macrocell - 64kbit Signalling Data
Input (D). The continuous stream of data to be output as 8 bit bursts during
timeslot 16 is input on this pin.
Digital ground,OV. (Note 2)
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