MV1403 Datasheet, PDF (8/18 Pages) Advanced Semiconductor – TUNING VARACTOR

MV1403
CLK
RXD1 B
B
RXD2
B
V
B
B
B
1 2 3 4 5 6 11 12
B
B
B
V
BV
V
B
Q
CDR
LIA
DV
NOTES:
1. B is a mark, V is a HDB3 violation.
2. There is a 5 period delay from input (RXD1/RXD2) to output (Q).
3. This diagram assumes that the rising edges of the RXD inputs occur at least 50ns before the rising edge of CLK.
Figure 8: HDB3 decoder timing - macrocell decoding HDB3 data and detecting errors
When in non CRC mode the international spare bit outputs,
Q1S and Q1N, represent data extracted from the bit position of
all sync frames and non-sync. frames respectively. If CRC
mode is enabled, these outputs now represent data extracted
from the bit 1 position of frames 13 and 15 respectively of the
CRC multiframe structure. In order to accomplish this, two
timing inputs, FRS13 and FRS15, are required. These inputs
are required to be high during bit 8 of the appropriate frame,
low during bit 8 of any other non-sync frame and any state
elsewhere. A final input to this macrocell, RST, may be used to
reset the synchronisation process, putting the macrocell out of
sync. Timing diagrams for the Timeslot Zero P(eceiver
macrocell are shown in Fig. 10.
Timeslot Sixteen Receiver
The Timeslot Sixteen Receiver macrocell extracts the 8
bits of common channel signalling data present in Timeslot 16
of successive frames of PCM data input on D. This 2.048Mbit
input data burst is stored and output as a continuous 64kbit
data stream. A single timing input, FRS, also common to the
CRCCHK macrocell, is required, this input being an 8 bit pulse
masking Timeslot Zero. Fig. 9 shows the timing of this
macrocell.
Cyclic Redundancy Checker
The Cyclic Redundancy Checker macrocell (CRCCHK)
performs a cyclic redundancy check procedure on the received
data in accordance with CCITT Recommendation G.704,
this procedure being performed on the data input on its D input
pin. The macrocell also extracts the first bit of each Timeslot
Zero (the first bit of each frame) and searches for the CRC
Multiframe Alignment Signal (MAS) in the bits from non-sync
frames.
When the MAS has been found the macrocell
synchronises to it. This process requires two timing inputs,
FRS and TZS. The FRS input must be high only during
timeslot zero and TZS must be high during timeslot zero of
sync frames.
The macrocell generates CRC words from the input data
and extracts the CRC bits being received in the first bit of sync
frames. Each generated CRC word is compared with the CRC
word received in the next sub-multiframe. Associated with this
process are three alarm outputs, MSA, ER1 and ER2. The
MSA (Multiframe Sync Alarm) output indicates whether
multiframe synchronisation has occured. It is high whilst the
macrocell is out of sync, and goes low after the beginning of
frame 11 in which a correct alignment pattern has been
received. The two error outputs, ER1 and ER2 indicate that
CRC errors were detected in submultiframes 1 and 2
respectively. These two outputs can only change state on the
first rising clock edge after the first bit of frames 0 and 8
respectively.
When in CRC multiframe alignment, the macrocell also
produces two timing outputs, FRS13 and FRS15, to reference
the positions of frames 13 and 15. These signals may be used
to allow the Timeslot Zero Receiver macrocell to extract the
international spare bits of these frames.
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