MV1403 Datasheet, PDF (12/18 Pages) Advanced Semiconductor – TUNING VARACTOR

MV1403
PIN DESCRIPTIONS (continued)
Symbol Pin No.
DP48 HP44
MFQ3 16
15
Mode
name
(see note 1)
RX
TX
MFQ4 17
16
RX
TX
MFQ5 18
17
RX
TX
FRS13RZ 19
18
RX1
RX2
MFD1 20
19
RX1
RX2
TX1
TX2
MFD2 21
20
RX1
RX2
TX
MFD3 22
21
RX
TX1
TX2
MFD4 23
22
RX
TX
V_DD3
24
-
GLOBAL
V_DD
_
23
Pin name and description
HDB3 Decoder (HDB3DC) Macrocell - Double Violation Alarm Output
(DV). This pin goes high one period after detection of a double violation on
either of the HDB3 inputs.
HDB3 Encoder (HDB3EC) Macrocell - Data Output (a). This output is a single
period delayed version of this macrocells D input.
HDB3 Decoder (HDB3DC) Macrocell - Clock Regeneration Output (CDR).
This output is a logical ‘OR’ function of the two HDB3 inputs and may be used
by external clock regeneration circuitry. This signal has a variable mark-to
space ratio.
HDB3 Encoder (HDB3EC) Macrocell - HDB3 Encoded Output 2 (TXD2). This
output is always low during the high half cycle of clock and is only high the
low half cycle if a mark is to be output.
HDB3 Decoder (HDB3DC) Macrocell - HDB3 Decoded Output (Q). This output
is the HDB3 inputs decoded back to NRZ form.
HDB3 Encoder (HDB3EC) Macrocell - HDB3 Encoded Output 1 (TXD1). As
TXD2 (MFQ4).
Timeslot Zero Receiver (RXTSZ) Macrocell - Frame 13 Marker Input (FRS13).
In CRC mode, this input should be high during bit 8, Frame 13 of the CRC
multiframe and low during bit 8 of all other non-sync frames.
This pin is unused since the FRS13 input ol the Timeslot Zero Receiver is
connected internally to the FRS13 output of the CRC Checker.
Timeslot Zero Receiver (RXTSZ) Macrocell - Frame 15 Marker input (FRS15).
In CRC mode, this input should be high during bit 8, Frame 15 ot the CRC
multiframe and low during bit 8 of all other non-sync frames.
This pin is unused since the FRS15 input of the Timeslot Zero Receiver is
connected internally to the FRS15 output of the CRC Checker.
No Connection.
PCM Voice Channel Input. In Transmit Demonstration mode this pin is used as
the serial data input to the Transmission Multiplexer.
Timeslot Zero Receiver (RXTSZ) Macrocell - Data Input (D). This pin is used
to input the 2.048 Mbit data stream to this macrocell.
This pin is unused since the D input of the Timeslot Zero Receiver is
connected internally to the Q output of the HDB3 Decoder.
Cyclic Redundancy Check Generator (CRCGEN) Macrocell - Signalling Data
Input (D1 N). This pin is used to input the data to be inserted into bit 1 of non
sync frames (CRC = 0) or bit 1 of frame 15 of the CRC multiframe (CRC = 1).
HDB3 Decoder (HDB3EC) Macrocell - Data Input 1 (RXD1). This input latches
the incoming HDB3 encoded data and is rising edge sensitive. The rising edge
of this input should not occur within 50 ns of the rising edge of CLK.
HDB3 Encoder (HDB3EC) Macrocell - Data Input (D). This pin is used to
input NRZ data for conversion into pseudo ternary HDB3 format.
This pin is unused since the D input of the HDB3 Encoder is connected
internally to the Q output of the Transmission Multiplexer.
HDB3 Decoder (HDB3DC) Macrocell - Data Input 2 (RXD2). As RXD1 (MFD3)
Cyclic Redundancy Check Generator (CRCGEN) Macrocell - Signalling Data
Input (D1S). This pin is used to input the data to be inserted into bit 1 of sync
frames (CRC = 0) or bit 1 of frame 13 of CRC multiframe (CRC = 1).
Digital supply voltage. 5V (Note 2)
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