MV1403 Datasheet, PDF (3/18 Pages) Advanced Semiconductor – TUNING VARACTOR

MV1403
FUNCTIONAL DESCRIPTION
The MV1403 PCM macrocell demonstrator contains a
family of 4 Transmit PCM and 4 Receive PCM macrocells
which may be configured to function individually, or be
connected together to form demonstrations of their operation.
In order to keep the pin count to a minimum, some of the input
and output pins are shared. Pin functions thus depend upon
whether the device is configured as a transmitter or receiver.
The operational modes of the MV1403 are selected under
control of the MODE and DEMO pins, as shown in Table 1.
Note that the MODE pin selects either the transmit or receive
set of macrocells and that the DEMO pins selects either
individual or combined connections.
In addition the operation of the MV1403 is controlled by a
further two control inputs, STM and CRC. The STM pin is used
for device testing and should be tied low for normal operation.
The CRC control pin selects whether or not the device-
performs the CRC generation/checking procedure. A logic
High’ on this pin puts the device in Cyclic Redundancy
Generate/Check mode.
More detailed information about all 8 macrocells can be
found in the individual macrocell publications.
INDIVIDUAL TRANSMIT MODE, TX1
In this mode (MODE = 0, DEMO = 0) the four transmitter
macrocells (TXTSZ, TXTS16, CRCGEN and HDB3EC) are all
accessed individually. The functional diagram of the MV1403
in this mode is shown in Fig. 2. All four macrocells are
synchronised to a common 2.048MHz clock, and the TXTSZ,
TXTS16 and CRCGEN macrocells are also synchronised to a
second timing input, FRS (Frame Sync). This is an 8 clock
period high going pulse at 8kHz which masks timeslot zero to
enable frame alignment. The function of each transmit
macrocell is now described separately.
TIMESLOT ZERO TRANSMITTER
The Timeslot Zero Transmitter macrocell generates a
Frame Alignment Signal (FAS) in accordance with CCITT
Recommendation G. 704. This is combined with the
international spare bit (the D1 input) and output on Q during
timeslot zero of alternate frames, denoted sync frames. During
the other interleaved frames, denoted non-sync frames, bit 2 is
fixed at logic 1 to avoid imitation of the FAS. This bit is slotted
together with the international spare bit (D1 input) and 6 user
data bits (the D3N-D8N inputs) for output on Q.
A TZS output (Timeslot Zero Sync frame) is provided to
denote whether a sync frame or non-sync frame is being
output. It changes state one clock period after the end of
timeslot zero and is high during timeslot zero of sync frames.
Fig. 3 shows the timing diagram for this macrocell.
TIMESLOT SIXTEEN TRANSMITTER
This macrocell takes in a continuous 64kbit data stream (D
input) and outputs it in 8 bit packets at a bit rate of 2.048 Mbit
during timeslot 16 of successive frames on its Q output. The
position of timeslot 16 is determined from the FRS timing input,
which masks timeslot zero. The TS16 output is an 8 clock
period high going pulse at 8kHz, similar to FRS, but high
during the 8 bits of timeslot sixteen.
Fig. 4 shows the timing diagram for this macrocell.
CYCLIC REDUNDANCY CHECK GENERATOR
This macrocell has two modes of operation, selected by its
EN control input. When EN is ‘high’, CRC generation mode is
selected. However, both modes are concerned with producing
the data bit to be inserted into the international spare bit of
timeslot zero (CCITT G. 704 structure). In non-CRC mode, this
data is selected to be either the D1S (sync frames) or DlN
(non-sync frames) input depending upon whether a sync or
non-sync frame is about to be transmined (determined by the
TZS input).
With CRC mode enabled, the macrocell generates CRC
words and outputs this data during the international spare bit of
sync frames. During non-sync frames, the 6 bit CRC
Multiframe Alignment Signal is output along with the two user
data inputs, DlS and D1N. This procedure is carried out in
accordance with CCITT Recommendation G. 704. The CRC
word is generated from the incoming data stream on the D
input pin. CCITT Recommendation G. 704 defines the 16
frame CRC multiframe structure, not related to the possible
use of a 16 frame multiframe structure in timeslot 16. Each 16
frame CRC multiframe is divided into two 8 frame sub-
multiframes, denoted submultiframes 1 and 2 (SMF1 and
SMF2). The CRC procedure is carried out on each sub-
multiframe of data and the resulting 4 bit CRC word is output
during the international spare bit of sync frames during the
following sub-multiframe. All data is output on the Q output pin.
Table 2 displays the CRC multiframe structure in more detail .
HIGH DENSITY BIPOLAR (HDB3 )ENCODER
The HDB3 Encoder macrocell converts the incoming NRZ
data on its D input pin into HDB3 pseudo-ternary form for
transmission over a 2.048 Mbit PCM link in accordance with
CCITT Recommendation G.703. The two TXD outputs
represent the HDB3 data in pseudo-ternary form. They are
always low during the high half cycle of CLK, but may be high
or low during the low half cycle. The Q output represents the D
input but delayed by one period. Fig. 5 shows the timing
diagram of this macrocell.
2