MV1403 Datasheet, PDF(7/18 Page) Advanced Semiconductor

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MV1403 Datasheet, PDF (7/18 Pages) Advanced Semiconductor – TUNING VARACTOR

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MV1403

INDIVIDUAL RECEIVE MODE, RX1

In this mode (MODE = 1, DEMO = 0) the MV1403 allows

access to the four receiver macrocells (HDB3DC, RXTSZ,

RXTS16 and CRCCHK) individually. The functional diagram

for the MV1403 in RX1 mode is shown in Fig. 7. The only

common connection between the macrocells is the 2.048MHz

clock used to synchronise the four macrocells. The function of

each individual macrocell is now described separately.

High Density Bipolar (HDB3) Decoder

The HDB3 decoder macrocell decodes the HDB3 pseudo-

ternary input data on its inputs, RXD1 and RXD2, into NRZ

form to be output on a This process is carried out in

accordance with CCITT Recommendation G. 703. In addition

the macrocell provides two alarm outputs, DV and LIA and a

clock recovery output, CDR.

The first of these, DV, is used to signal that a double

polarity violation has occurred on one of the pseudo-ternary

inputs, whilst the second, LIA (Loss of Input Alarm), signals

that eleven consecutive zeros have been received on the

inputs. The CDR output is provided to assist regeneration of

the 2.048MHz clock. This output is essentially just a logical

âORâ function of the two RXD inputs.

Since either a regenerated clock from the input data or a

clock local to the PCM receiver may be used to synchronise

the receiver, the two input signals cannot be guaranteed to

straddle a rising clock edge and as such the two inputs were

made asynchronous by the use of set-reset type latches

before the first synchronous storage elements on the inputs.

However, to ensure correct operation of the macrocell the

rising edge of either of the RXD inputs should not occur within

50ns of the rising edge of CLK. The timing diagram for this

macrocell is shown in Fig. 8.

Timeslot Zero Receiver

This macrocell is principally responsible for searching for

and locking on to the Frame Alignment Signal (FAS) present in

timeslot zero of the incoming data stream on the D input. This

process is carried out in accordance with the loss and recovery

of frame alignment strategy described in CCITT

Recommendation G.732. When frame alignment has been

achieved this macrocell outputs various timing reference

signals for use by the other macrocells and external circuitry.

The most important reference signal is the TSZ (Timeslot

Zero) output, which is equivalent to the FRS input signal

required by the transmitter macrocells. It is an 8 clock period

long active high pulse masking Timeslot Zero, allowing the

other macrocells to achieve frame alignment. This output will

free run when frame alignment is lost. The second timing

output is TZS (Timeslot Zero Sync. frame). This 4kHz signal

changes state once per frame, one period after the end of

Timeslot Zero to identify sync and non sync frames. The TZS

output is high during Timeslot Zero of sync frames.

Two timing outputs, CCR (Channel Reset) and CK8, are

not used by the other macrocells but may be used by external

circuitry. CCR is a low going pulse, one period wide, occurring

immediately after each timeslot zero sync frame. CK8 is an

8kHz signal going low at the end of bit 7 in each timeslot zero

and high at the end of bit 7 in each timeslot sixteen. The TZS,

CK8 and CCR outputs also free run when frame alignment is

lost.

Two alarm outputs are provided to signal errors in the

incoming data stream. The first of these, is an error alarm, ER,

which goes high for one frame following the frame in which a

Timeslot Zero sync word, containing a corrupted alignment

pattern, has been received. This alarm is only active whilst the

receiver is in sync. Note that three consecutive errors of this

type will put the receiver out of sync. Thus the second alarm

output, SA (Sync. Alarm), goes high when the receiver is out of

sync. In additon to the frame synchronisation process, the

Timeslot Zero Receiver is also responsible for extracting the

user data bits of non-sync words and the two international

spare bits. The former of these are accessed via the parallel

outputs Q3N-Q8N. The third bit of non-sync words (Q3N) is

used as the remote alarm bit from the transmitter and a third

alarm output RAI (Remote Alarm Indication), is derived from

this bit. This alarm is a persistence checked version of Q3N

and when the receiver is in sync, this alarm goes high when

two consecutive (Q3N bits have been received as high.

In order to extract the international spare bits of Timeslot

Zero, the macrocell must be in sync with CRC mode correctly

enabled or disabled. This is done using the M input with a logic

âhighâ on this pin putting the macrocell in CRC mode.

MFD4 MFD3 MFQ3

LIA MFQ4 MFQ5 MFD1 FRZ13RZ MFD2 Q1S, DQ1, DQ3-DQ8

LIA

CDR

Q1S, DQ1, DQ3-DQ8

RXD1

HDB3DC

RXD2

VDD

FRS13

RXTSZ

STM

DEMO

MODE

CLK

STM

DEMO

MODE

CLK

MODE

CONTROL

FRS15

RAI

TSZ

TZS

CK8

CCR

RST

M (CRC)

MFQ2

MFQ1

TSZRZ

TZSRZ

CK8

CCR

RST

CRC

TZS

MFDS

VDD GND

TZS

FRS

CRCCHK

RXTS16

FRS13

FRS

FRS13

MSA ER1 ER2

FRS

MFD6

MFQ9

Figure 7: RX1 individual receive mode functional diagram

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