MV1403 Datasheet, PDF (15/18 Pages) Advanced Semiconductor – TUNING VARACTOR

MV1403
ELECTRICAL CHARACTERISTICS
These characteristics are guaranteed over the following conditions (unless otherwise stated)
Supply Voltage V_DD = 5V ± 0 .V, Ambient Temperature T_amb = 0 to 70˚C
STATIC CHARACTERISTICS
Characteristic
Pin
Low level input voltage
High level input voltage
Low level output voltage
High level output voltage
Input leakage current
Supply current
Input capacitance
Output capacitance
V_IL
V_IH
V_OL
V_OH
I_IL
I_CC
C_IN
C_OUT
Value
Min
Typ
2.0
0
2.4
-20
-10
1.5
5
5
Max
0.8
V_DD
0.4
V_DD
-200
+10
3.0
Units
V
V
V
V
µA
µA
mA
pF
pF
Conditions
I_SINK = 10mA
I_SOURCE = 5mA
V_IN = V_SS
V_IN = V_DD
All outputs unloaded
DYNAMIC CHARACTERISTICS
Characteristic
Symbol
Value
Units
Min Typ Max
Conditions
Clock
Clock frequency
f_CLK
Clock rise time
t_CR
Clock high time
t_CH
Clock fall time
t_CF
Clock low time
t_CL
Outputs
Output propagation delay
CDR propagation delay
t_OPD
t_CDRPD
Frame synchronisation & related inputs
FRS rising hold time
FRS rising setup time
FRS falling hold time
FRS falling setup time
TZS setup time
TZS hold time
User data setup time
International data bits setup time
Timeslot Zero data hold time
t_FRH
t_FRs
t_FFH
t_FFS
t_SFS
t_SFH
t_UDS
I_IDS
t_TZDH
Data inputs
Data setup time
Data hold time
Timeslot 16 transmitter data setup time
Timeslot 16 transmitter data hold time
HDB3 input data setup time
HDB3 input data pulse width
t_DS
t_DH
t_T16DS
t_T16DH
t_RXDS
t_RXDW
2.048
20
150
20
150
MHz
ns
ns
ns
ns
50 ns
50 ns
50
ns
100
ns
50
ns
100
ns
50
ns
50
ns
50
ns
100
ns
100
ns
50
ns
50
ns
50
ns
50
ns
50
ns
50
488 ns
See Fig. 12
See Fig. 12
See Fig. 12
See Fig. 12
See Fig. 17, note 1
See Fig. 18
See Fig. 13
See Fig. 13
See Fig. 13
See Fig. 13
See Fig. 13
See Fig. 13
See Fig. 13
See Fig. 13
See Fig. 13
See Fig. 14, note 2
See Fig. 14, note 2
See Fig. 15, note 3
See Fig. 15, note 3
See Fig. 16
See Fig. 16
NOTES
1. The output propagation delay, t_OPD, is valid for all outputs except CDR (from the HDB3DC macrocell) and is specified with FRS
rising betore CLK. All output delays are measured with a 50pF load.
2. The data setup and hold parameters, t_DS and t_DH, apply to the following macrocell inputs: D (CRCGEN), D (HDB3EC) PCM
DATA (TMUX), D (RXTSZ), FRS13,15 (RXTSZ), RST (RXTSZ), D (RXTS16), D (CRCCHK), P (GLOBAL)
3. Timeslot 16 transmitter data setup and hold times apply to the rising edge of clock cycles 24, 56, 88 etc (see Fig 4)
ABSOLUTE MAXIMUM RATINGS
The Absolute Maximum Ratings are limiting values above which opertaing life may be shortened or specified parameters may be
degraded.
Positive supply voltage, V_DD
Inputs
Outputs
14
- 0.5 to + 7V
V_DD + 0.3V to GND - 0.3V
V_DD + 0.3V to GND - 0.3V