MV1403 Datasheet, PDF (14/18 Pages) Advanced Semiconductor – TUNING VARACTOR

MV1403
PIN DESCRIPTIONS (continued)
Symbol
RST
Pin No.
DP48 HP44
37
34
Mode
name
(see note 1)
RX
MFQ6 38
35
RX
TX
MFQ7 39
36
RX
TX
MFQ8 40
37
RX
TX
FRS15 41
38
RX
FRS13 42
39
RX
M FQ9 43
40
RX
TX
TSZRZ 44
41
RX
TZSRZ 45
42
RX
CK8 46
43
RX
CCR 47
44
RX
GND4 48
GND2 1
GLOBAL
Pin name and description
Timeslot Zero Receiver (RXTSZ) Macrocell - Reset Input (RST). A logic high
on this pin will reset the state machine of this macrocell, forcing the macrocell
out of frame alignment. Due to the 100kΩ pull-up resistors on all the inputs,
this pin should be tied low when not in use.
Cyclic Redundancy Checker (CRCCHK) Macrocell - Sub-multiframe 2 Error
Alarm Output (ER2). A logic high on this output indicates the detection of a
CRC error in sub-multiframe 2.
Cyclic Redundancy Check Generator (CRCGEN) Macrocell - Data Output (Q).
This pin is used to output the data to be inserted into bit 1, timeslot 0.
Cyclic Redundancy Checker (CRCCHK) Macrocell - Sub-multiframe 1 Error
Alarm Output (ER1). A logic high on this output indicates the detection of a
CRC error in sub-multiframe 1.
Cyclic Redundancy Check Generator (CRCGEN) Macrocell - Scan Test Data
Output (STQ). In scan test mode, this pin is the scan path output of this
macrocell.
Cyclic Redundancy Checker (CRCCHK) Macrocell - Multiframe Sync Alarm
Output (MSA). A logic high on this output denotes that the macrocell is out of
CRC multiframe alignment.
Timeslot Sixteen Transminer (TXTS16) Macrocell - Timeslot 16 Marker Output
(TS16). This output is high only during timeslot 16.
Cyclic Redundancy Checker (CRCCHK) Macrocell - Frame 15 Marker Output
(FRS15). When the macrocell is in CRC multiframe alignment, this output is
high during frame 15 and low during all other non-sync frames.
Cyclic Redundancy Checker (CRCCHK) Macrocell - Frame 13 Marker Output
(FRS13). When the macrocell is in CRC multiframe alignment, this output is
high during frame 13 and low during all other non-sync frames.
Timeslot Sixteen Receiver (RXTS16) Macrocell - Signalling Data Output
(Q). This pin is used to output the 8 bits of signalling data extracted from
timeslot 16 as a continuous 64kbit data stream.
Timeslot Sixteen Transmitter (TXTS16) Macrocell - Signalling Data Output (Q).
The 8 bit data bursts produced by this macrocell are output at 2.048MHz on
this pin during timeslot 16. This output is low at all other times.
Timeslot Zero Receiver (RXTSZ) Macrocell - Timeslot Zero Marker Output
(TSZ). This output goes high for the 8 periods of timeslot zero and is low at
all other times.
Timeslot Zero Receiver (RXTSZ) Macrocell - Timeslot Zero Sync Frame
Marker Output (TZS). This output is high during timeslot zero of sync frames
and changes state at the beginning of bit 2, timeslot 1 of every frame.
Timeslot Zero Receiver (RXTSZ) Macrocell - 8kHz Clock Output (CK8). This
output goes low at the end of bit 7, timeslot zero and high at the end of bit 7,
timeslot 16.
Timeslot Zero Receiver (RXTSZ) Macrocell - Channel Reset Output (CCR).
This output pulses low for a single period during bit 1, timeslot 1 of sync
frames.
Digital ground. 0V (Note 2).
NOTES
1. TX refers to TX1 and TX2 modes. RX reters to RX1 and RX2 modes. GLOBAL refers to all modes.
2. All the V_DD and GND pins of the 48-pin device, and two GND pins of the 44-pin device are connected together internally and
as such there is no need to connect up all these supplies. However, it is recommended that all supply pins are connected to
facilitate supply decoupling.
3. Since the device is intended as a demonstrator allowing access to the individual macrocells, 100kΩ pull-up resistors have
been included on all the input pins to prevent any unconnected inputs from floating.
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