MT90502 Datasheet, PDF (61/191 Pages) Zarlink Semiconductor Inc – Multi-Channel AAL2 SAR

Preliminary Datasheet
MT90502
SSRAM MapCpPinSg--PMaPcDkQetSpDaecsecriptor Queue Structures
+ _0000h
+ 0040h
+ 0080h
+ 00C0h
+ _0100h
HDLC Stream 0 CMPPSDPQDQ
HDLC Stream 1 CMPPSDPQDQ
HDLC Stream 2 CMPSDPQDQ
HDLC Stream 3 CMPPSDPQDQ
HDLC Stream 4 CMPPSDPQDQ
+(N-3) * 4 0h
+(N-2) * 40h
+(N-1) _{* 40h}
HDLC Stream N-3 CMPPSDPQDQ
HDLC Stream N-2 CMPPSDPQDQ
HDLC Stream N-1 CMPPSDPQDQ
+0
MCPinSi-Packet Descriptor 0
+4
MCPinSi-Packet Descriptor 1
+8
MCPinSi-Packet Descriptor 2
+34 MCiPnSi--Packet Descriptor 13
+38 MCiPnSi-Packet Descriptor 14
+3C MCPinSi-Packet Descriptor 15
NCPumSPbeDN5r1Quo2mf,sbH1ter0Dur2cLo4tCfu} _{HrSeDtsrLeaCarmeSstr6e(4sa-ambryscte(asspaarinc_ictyas)ipzaiesciNltoy)c=ais1te2Nd8C=,Pi2n{S15-2S6P8,aS,c}5R2_k1_{eA52t6M,,10m2e3m. ory at addresses +4000h to +5FC0h,}
+8000h to +BFC0h, +10000h to +17FC0h and +20000h to +2FFC0h for 128, 256, 512 and 1023 channels
respectively.
This structure is used by Hardw_Ma_inre_i-Pon_al_cy_k. _{et Descriptor Structure}
b15 b14 b13 b12 b1^C1 ^Pb^S10^-Pab^c9^keb^t 8^Deb^s7^cripb^t6^or b^S5^trub^c4^tureb3 b2 b1 b0
+0 bM15inib-P1a4ckbe1t3Dibsa1s2sebm11blybS1t0rctb. 9Nubm8[9b:07] b6 b5 b4 b3 b2 b1 b0
+0 CPS-Packet Disassembly Strct. Num[9:0]
++22
M_Cin_Pi_S-P_-a_Pc_ak_ce_kt_eB_t a_Bs_ae_sA_ed_Ad_dd[_[9₉:1_:1]_]
Lengt^Lh^e[6ⁿ:^g0^t]^h[6:0]
Reserved
CMPinSi-Packet Disassembly Struct. Num : InIdnidciacatetesswwhhicichhCMPCSPinSi--PPaacket disassembly structure
this MCPinSi-Packet comes from. This will identify the circular buffer in which it is written.
CMPinSi-Packet Base Add : Points to the first byte of the MCiPniS-P-Paacckkeettwithin the circular buffer.
Length: Length of the mCPinSi--pPaaccket, in bytes. Valid range 01h (1- byte) to 40h (64- bytes).
Figure 33 - CPS-Packet Descriptor Queue Structures (HDLC Streams)
As HDLC supports streams, numerous channel packet descriptor queues can be amalgamated into one packet
descriptor per stream. However, it is necessary to specify the length of the packet descriptor queue within the
structure that manages the stream; therefore, the MT90502 can determine where to wrap its read and write
pointers. The length of the packet descriptor queue is programmed by the CPU/Software in the HDLC control
structure (see Figure 30, “RX TDM Control Memory Structure (PCM/ADPCM channels),” on page 58). The
CPS-Packet disassembly structures in the RX SAR determine where the HDLC channels are destined.
In HDLC, time slot entries in the linked list can point to the same control structure entry, allowing the HDLC
single-channel or stream to span consecutive time slots within the same TDM stream. This is employed for
HDLC streams where the bandwidth requirements often exceed the constraints of a single time slot. Since
multiple entries pointing to the same HDLC channel must all be contained within the same TDM stream, the
maximum number of time slots that can be shared by the same HDLC channel is 128.
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