MT90502 Datasheet, PDF (180/191 Pages) Zarlink Semiconductor Inc – Multi-Channel AAL2 SAR

MT90502
Preliminary Datasheet
read_access_active
(when both CS, DS are low
and R/W is high)
cpu_ale
cpu_d[15:0]
cpu_rdy_ndtack
t15
t1
t3_muxed
t17
t16
t12
t8
t5
t11
t9
t14
t10
t3_reads
Figure 78 - Multiplexed CPU Interface - Motorola Mode - Read Access
Symbol
Description
Min Typical Max Unit
t1 read_access_active falling edge to cpu_ale fall
2 * upclk - 4 ns
t3_muxed cpu_rdy_ndtack falling edge to cpu_ale rising edge
0
ns
t3_reads cpu_rdy_ndtack falling edge to read_access_active rising
0
ns
edge
t5 Read Access Time
see
Table 205
t8 read_access_active falling edge to cpu_d driven
3 * upclk - 4
ns
t9 read_access_active falling edge to cpu_rdy_ndtack driven
0
high
12
ns
t10 read_access_active rising edge to cpu_rdy_ndtack rising
0
edge
10
ns
t11 cpu_rdy_ndtack rising edge to cpu_rdy_ndtack tri-state
2
8
ns
t15 cpu_ale high pulse width
5
ns
t16 cpu_d valid to cpu_ale falling edge
5
ns
t17 cpu_ale falling edge to cpu_d invalid
5
ns
Table 209 - Multiplexed CPU Interface - Motorola Mode - Read Access
180