MT90502 Datasheet, PDF (110/191 Pages) Zarlink Semiconductor Inc – Multi-Channel AAL2 SAR

MT90502
Preliminary Datasheet
Address: 17Eh
Label: chip_and_revision
Reset Value: 0101h
Label
Bit Position
chip_id[7:0]
7:0
rev_id[7:0]
15:8
Type
RO Chip ID = 01h.
RO Revision ID = 01h.
Table 44 - ID Register
3.2
Main Registers
Description
Address: 202h
Label: status0
Reset Value: 0000h
Label
mema_sdram_parity_error0
mema_sdram_parity_error1
memb_sdram_parity_error0
memb_sdram_parity_error1
mema_ssram_parity_error0
mema_ssram_parity_error1
memb_ssram_parity_error0
memb_ssram_parity_error1
memb_bad_cpu_access
sdrama_too_late
sdramb_too_late
reserved
Bit Position Type
Description
0
ROL Parity error on the high byte of bank A SDRAM.
1
ROL Parity error on the low byte of bank A SDRAM.
2
ROL Parity error on the high byte of bank B SDRAM.
3
ROL Parity error on the low byte of bank B SDRAM.
4
ROL Parity error on the high byte of bank A SSRAM.
5
ROL Parity error on the low byte of bank A SSRAM.
6
ROL Parity error on the high byte of bank B SSRAM.
7
ROL Parity error on the low byte of bank B SSRAM.
8
ROL Indicates that an access was attempted to bank B when
the bank was not present.
9
ROL Indicates that bank A SDRAM cannot refresh quickly
enough. Information in that memory may be corrupt.
10
15:11
ROL Indicates that bank B SDRAM cannot refresh quickly
enough. Information in that memory may be corrupt.
ROL Reserved. Always read as “0000_0”
Table 45 - Main Status Register
110