MT90502 Datasheet, PDF (123/191 Pages) Zarlink Semiconductor Inc – Multi-Channel AAL2 SAR

Preliminary Datasheet
MT90502
Address: 250h
Label: sdram_conf0
Reset Value: 0000h
Label
Bit Position Type
Description
sdrama_enable
sdramb_enable
sdrama_manual_access
sdramb_manual_access
sdrama_size
sdramb_size
sdram_refresh_freq
reserved
0
RW When '0', the values placed in the sdram_conf3 register will be
placed on the SDRAM A pins.
1
RW When '0', the values placed in the sdram_conf3 register will be
placed on the SDRAM B pins.
2
PUL When written to 1 and sdrama_enable is '0', the values placed
in the sdram_conf4 register will be placed on the SDRAM A
pins.
3
PUL When written to 1 and sdramb_enable is '0', the values placed
in the sdram_conf4 register will be placed on the SDRAM B
pins.
4
RW 0' = 4M x 16 (8 Megabytes), '1' = 8M x 16 (16 Megabytes)
5
RW 0' = 4M x 16 (8 Megabytes), '1' = 8M x 16 (16 Megabytes)
7:6
RW “00” = 1 refresh every 16 cycles, “01” = 1 refresh every 8
cycles, “10” = 1 refresh every 4 cycles. Typical value “00”.
15:8
RW Reserved. Must always be “0000_0000”.
Table 63 - SDRAM Configuration Register 0
Address: 252h
Label: sdram_conf1
Reset Value: 0400h
Label
sdram_refresh_cnt
Bit Position Type
Description
15:0
RW Number of mem_clk cycles per refresh to the SDRAM.
Table 64 - SDRAM Configuration Register 1
Address: 254h
Label: sdram_conf2
Reset Value: 0200h
Label
sdram_max_lateness
Bit Position Type
Description
15:0
RW Maximum number of refreshes that the SDRAM can be late
before reporting an error.
Table 65 - SDRAM Configuration Register 2
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