MT90502 Datasheet, PDF (4/191 Pages) Zarlink Semiconductor Inc – Multi-Channel AAL2 SAR

MT90502
Preliminary Datasheet
2.6.2 UTOPIA Interfaces............................................................................................................................... 63
2.6.3 LED Operation ..................................................................................................................................... 63
2.6.4 Errors on Received Cells ..................................................................................................................... 63
2.6.5 Cell Routing ......................................................................................................................................... 64
2.6.5.1 Mask & Match Process .................................................................................................................. 64
2.6.5.2 Look-Up Tables Entries ................................................................................................................. 65
2.6.5.3 LUT Addressing ............................................................................................................................. 66
2.6.6 UTOPIA Clocks.................................................................................................................................... 67
2.6.7 External Interface Signals.................................................................................................................... 69
2.6.8 UTOPIA Flow Control .......................................................................................................................... 69
2.7 H.100/H.110 Interface ................................................................................................................................70
2.7.1 Overview.............................................................................................................................................. 70
2.7.2 Bus Signaling....................................................................................................................................... 70
2.7.3 H.100/H.110 Slave............................................................................................................................... 70
2.7.4 Operating as a Slave ........................................................................................................................... 71
2.7.5 Operating as a Master ......................................................................................................................... 71
2.7.6 H.100/H.110 Clock Selection Guide .................................................................................................... 72
2.8 Clock Recovery ..........................................................................................................................................75
2.8.1 Overview.............................................................................................................................................. 75
2.8.1.1 Adaptive Clock Recovery Modules ................................................................................................ 75
2.8.1.1.1 adapx_ref clock generation ...................................................................................................... 75
2.8.1.2 Multiplexers .................................................................................................................................... 75
2.8.2 Adaptive Clock Recovery Modules ...................................................................................................... 75
2.8.2.1 adapx_ref Clock Generation .......................................................................................................... 78
2.8.3 Multiplexers.......................................................................................................................................... 78
2.9 Silence Suppression ..................................................................................................................................83
2.9.1 Overview.............................................................................................................................................. 83
2.9.2 Simple Silent Suppression................................................................................................................... 83
2.9.2.1 Silent Bit Indication ........................................................................................................................ 83
2.9.2.2 Last Byte Indication ........................................................................................................................ 83
2.9.2.3 Match and Mask Determines Silence ............................................................................................ 83
2.9.3 Complex Silent Suppression................................................................................................................ 84
2.9.3.1 Complex Silent Suppression Operation ......................................................................................... 85
2.9.3.1.1 PCM Law Table ........................................................................................................................ 85
2.9.3.1.2 DC Offset Calculation ............................................................................................................... 86
2.9.3.1.3 Signal Energy Calculation ........................................................................................................ 86
2.9.3.2 CPS-Packet Silence State ............................................................................................................. 87
2.9.3.2.1 Silence Suppression State Table ............................................................................................. 87
2.9.3.2.2 SID Transmission Operation .................................................................................................... 87
2.9.3.2.3 SID Reception Operation ......................................................................................................... 87
2.9.4 Voice/Silence Timer............................................................................................................................. 90
2.10 HDLC .......................................................................................................................................................94
2.10.1 HDLC Overview ................................................................................................................................. 94
2.10.2 HDLC Format..................................................................................................................................... 94
2.10.3 HDLC Bit-Wise Format ...................................................................................................................... 97
2.10.4 HDLC Byte-Wise Format ................................................................................................................... 97
2.11 Memory ....................................................................................................................................................97
2.11.1 Memory Map...................................................................................................................................... 97
2.11.2 Memory Structures ............................................................................................................................ 98
2.11.3 Mem_Clk and Upclk......................................................................................................................... 103
2.11.4 Memory Controller ........................................................................................................................... 104
2.11.4.1 Overview .................................................................................................................................... 104
2.11.4.2 Functionality ............................................................................................................................... 104
2.11.5 Initializing SSRAM and SDRAM ...................................................................................................... 104
2.11.6 Memory Configuration ..................................................................................................................... 105
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