MT90502 Datasheet, PDF (36/191 Pages) Zarlink Semiconductor Inc – Multi-Channel AAL2 SAR

MT90502
Preliminary Datasheet
CPS-Packet Final Assembly Structure (HDLC Channel)
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
+0h
VC Number [9:0]
Pack Del Cnt[3:0]
+2h
CID
SUI Send UUI [3:0]
+4h
+6h
+8h
+Ah
+Ch
+Eh
+1h
+12h
+14h
+16h
+18h
CPS-Packet Byte Count [31:16]
+1Ah
CPS-Packet Byte Count [15:0]
+1Ch
CPS-Packet Count [31:16]
+1Eh
CPS-Packet Count [15:0]
Fields in Italic are used by hardware only. Fields in Plain are
written to by the CPU/Software.
CPS-Packet Final Assembly structures are fixed and are located in
TX SSRAM memory at addresses +1000h to +1FE0h, +2000h to
+3FE0h, +4000h to +7FE0h and +8000h to +FFE0h for 128, 256,
512 and 1023 channels respectively.
Each structure is 32-bytes in size.
VC Number: Number of the VC in which the CPS-Packets of
this AAL2 Channel will be routed.
Packet Delete Count: Indicates the number of packets that
must be deleted (not sent) before the AAL2 Channel starts. 0
means send immediately. 15 means never send. 1 to 14
mean delete the first 1 to 14 first CPS-Packets generated. At
start-up, this field may be set to 1 or more in order to never
send garbage on an AAL2 Channel.
CID: Channel ID on AAL2 VCs that will be annexed to the
CPS-Packets.
Send UUI: Send this UUI value. These are the four lower bits
of the UUI that will be sent in all AAL2 CPS-Packets. The 0 to
4 lower bits of this field can be substituted by the 0 to 4 lower
bits of the CPS-Packet Count, depending on the Send UUI
Increment Field.
SUI: Send UUI Increment. When “000” = 4 bits used as
counter, “001” = 3 bits used as counter, “010” = 2 bits used as
counter, “011” = 1 bit used as counter, “100” = 0 bits used as
counter, “101” = send the UUI value contained in the HDLC
CPS-Packet control byte. Others = reserved. Once in “raw”
CPS-Packet mode, Send UUI and SUI are ignored.
CPS-Packet Byte Count: Byte counter of all payload bytes
sent (payload is defined as the LI+1 in each CPS-Packet).
CPS-Packet Count: CPS-Packet counter of all sent packets.
Figure 16 - CPS-Packet Final Assembly Structure (HDLC Channel)
2.2.4.1 CPU CPS-Packets
The TX TDM module allows the generation of CPU sourced CPS-Packets. When the CPU requires to transmit
an AAL2 CPS-Packet onto a certain VC, it programs the VC number in register 520h, and writes the
CPS-Packet's descriptor structure in registers 522h to 526h. The format of the CPS-Packet descriptor structure
is given in Figure 17. Word 0 must be written into register 522h, Bytes +2 and +5 to register 524h and Bytes +4
and +5 to register 526h. Finally, it writes a '1' to the cps_packet_request bit in register 520h, which begins the
request. When the bit clears, the process has concluded and the CPS-Packet has been added to the TX VC's
queue.
The following process is used to send a CPU CPS-Packet:
1) The payload of the CPS-Packet must be written into some unused portion of the external SSRAM (bank A).
The format for writing the payload to memory is shown in the following example. In the example, the
CPS-Packet payload is 25-bytes.
address
bits [15:8]
bits[7:0]
cpsp_base + 0 (word 0):
payload 0
payload 1
cpsp_base + 2 (word 1):
payload 2
payload 3
...
...
...
cpsp_base + 24 (word 12):
payload 24
xxxxxxxx
Table 19 - Format for writing CPS-Packet payload to memory
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