GP4020 Datasheet, PDF (6/17 Pages) Zarlink Semiconductor Inc – GPS Receiver Baseband Processor

GP4020
Pin No. Signal name
Type
Associated
circuit block
Description
Notes
89 TMS/bdiag[3]/XCon I/O
JTAG/SSM JTAG Test Mode Select/SSM Diagnostic 6
broadcast debug output bdiag[3]/System test
control input XCon.
90
NTRST
I
JTAG/SSM JTAG interface Reset or SSM debug interface 6
multiplex (pins 86, 87, 88 and 89).
91 GPI0[7]/PLLDT1
I/O GPIO/SCG PLL General Purpose Input/Output 7. Can be 3
multiplexed to SCG PLL Digital Test Output
(PLLDT1).
92
GPIO[6]
I/O
GPIO
General Purpose Input/Output 6.
3
93 GPIO[5]/DISCOP
I/O
GPIO/CORR General Purpose Input/Output 5. Can be 3
multiplexed to DISCOP discrete output from
correlator.
94
GND
PWR
95 GPIO[4]/DISCIP1
I/O
GPIO/CORR General Purpose Input/Output 4. Also directly 3
connects to DISCIP1 on the 12-channel correlator.
96 GPIO[3]/BSIO_SS[1] I/O
GPIO/BSIO General Purpose Input/Output 3. Can be 3
multiplexed to BSIO Slave Select[1].
97 GPIO[2]/BSIO_SS[0] I/O
GPIO/BSIO General Purpose Input/Output 2. Can be 3
multiplexed to BSIO Slave Select[0].
98
V_DD
PWR
99 GPIO[1]/BSIO_DATA I/O
GPIO/BSIO General Purpose Input/Output 1. Can be 3
multiplexed to BSIO Data Input/Output.
100 GPIO[0]/BSIO_CLK I/O
GPIO/BSIO General Purpose Input/Output pin 0. Can be 3
multiplexed to BSIO_CLK output.
Table 1 - Pin descriptions (continued)
NOTES
1. High impedance is achieved on pins 11 to 18, 20, 21, 23 to 29, 31, 32, 34 to 37 when either:
(a) Data is not being written from GP4020.
(b) POWER_GOOD (pin 64) is low.
(c) Bit 1 (RF_PD) of POW_CNTL register is high.
(d) Bit 10 (RF_SLEEP) of POW_CNTL register is high.
2. NSUB (pin 52) is the Upper Byte select output from the Memory Peripheral Controller, when single chip 16-bit
memories with NUB and NLB inputs are used. NSUB maps to NUB and address line SADD[0] to NLB.
3. Input is tolerant to being driven with a +5V HIGH level, as well as +3·3V HIGH nominal level.
4. Both CLK_T (pin 58) and CLK_I (pin 59) should not have an external DC bias of GREATER than +1·7V . Direct
connection from a GP2010/GP2015 RF front end is NOT possible, without bias-shift circuit (Figure 3).
5. TEST (pin 67) and TESTMODE (pin 74) are used together to set up manufacturing test modes for the GP4020,
as shown in Table 2 (0 = GND, 1 = V_DD).
TEST TESTMODE
(pin 67) (pin 74)
Test function
0
0
Normal operation
1
0
Firefly Macrocell test mode
0
1
Firefly System test mode
1
1
UIM logic test mode
Table 2 - Test mode truth table
Details of ALL test modes are covered in section 2.10 of the Zarlink Semiconductor Firefly MF1 Core Design
Manual.
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