GP4020 Datasheet, PDF (13/17 Pages) Zarlink Semiconductor Inc – GPS Receiver Baseband Processor

GP4020
Electrical Characteristics (continued)
Characteristic
Symbol
Min.
Value
Typ. Max.
Units
Conditions
40MHz Low Level Differential Input
Input voltage bias
Differential input voltage
Input differential hysteresis
Input clock frequency
Input capacitance
Power-on delay
Processor Clock Oscillator
Frequency
Start up time
Mark:space
Transconductance
Output impedance
Feedback resistance
Phase Locked Loop
Input frequency
Output frequency
Duty cycle
Phase alignment offset (falling edges
of CLKINB, CLKFBKB)
Phase Alignment Jitter
Phase Jitter
CLKINB to CLKOUTB delay
PLL Settling Time
Real Time Clock
Crystal frequency
Start up time
Transconductance
Output impedance
Feedback resistance
BµILD Serial Input / Output (BSIO)
3-wire Bus Interface
BSIO_CLK output frequency
Serial clock output low period
Serial clock output high period
Serial clock output rise time
Serial clock output fall time
Serial data output delay
Serial enable output delay
Serial chip select enable to first clock
edge delay
Serial last clock edge delay to chip
select disable
V_DBIAS
0
1·715 V
V_DIFIN
100
mV
V_DIFHYS 12
24 mV
F_DIFIN
40 150 MHz
C_DIFIN
5
pF
150 ns
F_PRXIN
T_PRXSU
g_m
Z_O
R_F
10
10
45 50
1·0 2·24
93
220
16 MHz
ms
55 %
4·4 mA/V
kΩ
kΩ
F_PLLIN
10
F_PLLOUT 10
20 MHz
250 MHz
45 50 55 %
+-0·2 ns
T_PLLSET
F_RTC
T_RTCSTART
G_MRTC
Z_ORTC
R_FRTC
+-0·25 ns
+-0·15 ns
0·43
ns
147
µs
32·768
400
9·56
422
10
kHz
ms
µA/V
MΩ
MΩ
F_SEROF
T_SERCL
T_SERCH
T_SERCR
T_SERCF
T_SERDOD
T_SEREOD
T_SERCDC
40
40
-20
-20
70
T_SERCEC 70
10 MHz
ns
ns
10 ns
10 ns
20 ns
20 ns
ns
ns
Min. V_DD = 3·0V Note 1
40MHz from RF front end
Not including package
Correct external components
Across frequency range
Across all conditions
Can be divided down by 1,2,4 or
8 for optimal BµlLD_CLK freq.
Note 2
Cycle-cycle edge jitter Note 2
In clock bypass mode
In clock synchronisation mode
Correct external components
Across frequency range
External component
SEROUT ref SERCLK
SERSEL ref SERCLK
NOTES
Cont…
1. The input pair CLK_T, CLK_I may be driven by a low amplitude differential sinewave from an RF Front-end.
Direct DC connection to a GP2010 or GP2015 RF front end is NOT possible, as the maximum DC bias from these
devices is in excess of maximum input bias limit.
2. Jitter is dominated by supply-noise effects. Users must keep on-chip supply noise below 1Vp-p by the use of
low noise outputs and as many supply pins as possible.
13