GP4020 Datasheet, PDF (5/17 Pages) Zarlink Semiconductor Inc – GPS Receiver Baseband Processor

GP4020
Pin No. Signal name
Type
Associated
circuit block
Description
Notes
60
GND
PWR
61
SIGN0
I
62
MAG0
I
63
SAMPCLK
O
64
POWER_GOOD
I
65
PR_XOUT
O
66
PR_XIN
I
67
TEST
I
68
V_DD
PWR
69 TIMEMARK / TIC
O
70
IDDQTEST
I
71
GND
PWR
72
RTC_XIN
I
73
RTC_XOUT
O
74
TESTMODE
I
75
NSRESET
I
76
U2TXD
O
77
U2RXD
I
78
U1TXD
O
79
U1RXD
I
80
PLLGND
PWR
81
PLLVDD
PWR
82
GND
PWR
83
PLLAT1
O
84
NICE
I
85
V_DD
PWR
86 TCK/bdiag[0]/XReq I/O
87 TDI/bdiag[1]/XWrite I/O
88 TDO/bdiag[2]/XBurst I/O
CORR
CORR
CORR
PCL
SCG
SCG
Sampled Sign (polarity) data from RF front end.
Sampled Mag (amplitude) data from RF front
end.
Sample Clock output to the RF front end. Provides
a 5·714MHz clock with a 4:3 mark to space ratio.
Power Monitor input, high for normal operation;
low forces the GP4020 into Power Down mode.
System Clock Oscillator - crystal output for 10 to
16MHz crystal.
System Clock Oscillator - crystal inputfor 10 to
16MHz crystal.
TEST select pin,used with TESTMODE (pin 74). 5
Used for test purposes only and should be
connected to GND in normal operation.
1PPS
Timemark output. This pin can be used to produce
a UTC-aligned 1 PPS output, or TIC output.
TEST select pin,used with TESTMODE (pin 74).
Used for test purposes only and should be
connected to GND in normal operation.
RTC
RTC
PCL
UART2
UART2
UART1
UART1
SCGPLL
SCGPLL
Real-time Clock Oscillator input for 32kHz crystal.
Real-time Clock Oscillator output for 32kHz crystal.
TEST select pin,used with TEST (pin 67). Used 5
for test purposes only and should be connected
to GND in normal operation.
System Reset input.
UART 2 Transmit data output.
UART 2 Receive data input.
3
UART 1 Transmit data output.
UART 1 Receive data input.
3
GND connection for PLL Block.
V_DD connection for PLL Block.
SCGPLL System Clock Generator PLL Analog Test I/O.
Reserved for TEST purposes only and should
NOT be connected in normal operation.
JTAG/SSM ARM7 operating mode and JTAG / SSM Signal 6
MUTIPLEX Multiplex (pins 86, 87, 88, 89).
JTAG/SSM JTAG Test Clock/SSM Diagnostic broadcast 6
debug output bdiag[0]/System test control input
XReq.
JTAG/SSM JTAG Test Data In/SSM Diagnostic broadcast 6
debug output bdiag[1]/System Test control input
X/Write.
JTAG/SSM JTAG Test Data Out/SSM Diagnostic broadcast 6
debug output bdiag[2]/System test control input
XBurst.
Table 1 - Pin descriptions (continued)
Cont…
5