GP4020 Datasheet, PDF (11/17 Pages) Zarlink Semiconductor Inc – GPS Receiver Baseband Processor

GP4020
Since the memory is high-speed, it can be accessed
with Zero wait-states through the Memory Peripheral
Controller. Refer to section on the Memory Peripheral
Controller for more information.
Real Time Clock (RTC)
The GP4020 Real Time Clock uses an external 32kHz
crystal to give an indication of time to the GP4020 chip,
when the device is in Reset / Power Down. If a backup
battery is included in a GPS receiver using the GP4020,
the RTC will continue to operate regardless of the reset
state of the rest of the device.
The RTC is incremental, which means that the number
of seconds from a reset point are accumulated, rather
than a record of Gregorian date.
System Clock Generator (SCG)
The GP4020 System Clock Generator is used to
provide 2 system clocks:
• The M_CLK for the 12-channel Correlator; this is
derived from the CLK_T and CLK_I inputs from the
RF front end device and MUST be 40MHz. This
clock is fundamental to the correlator function, and
must be phase-locked to the RF front end.
• The BµILD_CLK for ALL components on the BµILD
Bus; this can be derived from M_CLK (see above) in
conjunction with a PLL and a divider to generate a
wide range of clock frequencies. In this way, the
BµILD_CLK can be phase-locked to the RF front end.
The clock can also be derived from an independent
crystal source.
System Services Module (SSM)
The System Services Module (SSM) ensures correct
bus operation through a number of modes (reset,
initialisation, debug, etc). It provides diagnostic
broadcast of address and data for internal transfers
along with information about the current operating
mode.
Additionally the SSM System Configuration Register
controls the operating mode of the GP4020.
Specifically the System Services Module performs the
following functions:
• Control the BµILD bus operational mode
• Arbitrate amongst competing resources for BµILD
bus mastership
• Interface to external bus masters and
manufacturing testers
• Control the activities of all BµILD bus modules during
system debug activity.
• Broadcast information about BµILD bus activity for
external diagnostics
• Hold BµILD bus logic levels when no other bus-
master is driving
• Register System Configuration data
System Timer/Counters (SYSTIC)
Two dual independent 32-bit timer/counters, with an 8-
bit pre-scaler capability for each counter, are provided
(Timers 1A, 1B, 2A and 2B). These are synchronous to
the system clock and may be polled, or set-up to
generate interrupts on over-run, with auto-reload.
The TIC functions provided by this module are part of
the Firefly MF1 core. Timer 1 (TIC1) appears at GP4020
Base Address 0xE000 E000, and Timer 2 (TIC2)
appears at Address 0xE000 F000. TIC enable (TEN)
lines are not available externally on this version of the
GP4020, but are tied low on-chip. The TIC functions can
be made available by setting the External enable
polarity bit of the TIC Control/Status register to a logic
‘0’.
Whilst these timer/counters are NOT required by the
GPS function in a GP4020 based GPS receiver, full
programming details of the programming of the System
Timer/Counter can be found in Section 7 of the Firefly
MF1 Core Design Manual.
1PPS Timemark Generator
The GP4020 Timemark generator is used in conjunction
with software to produce a 1 Pulse Per Second (1PPS)
output pulse, which is aligned to Universal
Time Co-ordinated (UTC) to a resolution of 25ns. The
accuracy of time transmitted from the Navstar GPS
space segment is very high, and this can be used to
provide a mobile timing reference to a similar accuracy.
Up Integration Module (UIM)
The Up Integration Module provides a series of internal
connection ports, which mimic the MPC external
interface. This allows the Firefly MF1 to communicate
with the Application Specific Logic used in the GP4020,
as though it was external to the chip, hence it acts as a
transparent interface.
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