GP4020 Datasheet, PDF (3/17 Pages) Zarlink Semiconductor Inc – GPS Receiver Baseband Processor

GP4020
76
50
100
1
25
Figure 2 - Pin connections (top view)
QPA100
Pin No. Signal Name
Type
Associated
circuit block
Description
Notes
1
SADD[0]
I/O
MPC
System Address bit 0
2
SADD[1]
I/O
3
SADD[2]
I/O
4
SADD[3]
I/O
5
SADD[4]
I/O
6
SADD[5]
I/O
7
GNDPWR
8
SADD[6]
I/O
9
SADD[7]
I/O
10
V_DD PWR
11
NSCS[0]
I/O
12
NSCS[1]
O
13
NSCS[2A]
O
14
SADD[19]
O
15
SDATA[0]
I/O
16
SDATA[1]
I/O
17
SDATA[2]
I/O
18
SDATA[3]
I/O
19
GNDPWR
20
SDATA[4]
I/O
21
SDATA[5]
I/O
22
V_DD PWR
23
SDATA[6]
I/O
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
MPC
System Address bit 1
System Address bit 2
System Address bit 3
System Address bit 4
System Address bit 5
System Address bit 6
System Address bit 7
System Chip Select 0 - Active Low
1
System Chip Select 1 - Active Low
1
System Chip Select 2A - Active Low 1
System Address bit 19
System Data bit 01
System Data bit 11
System Data bit 21
System Data bit 31
System Data bit 41
System Data bit 51
System Data bit 61
Table 1 - Pin descriptions
Cont…
All V_DD and GND pins must be connected to ensure reliable operation. Any unused input pins must be tied either
high or low; no inputs should be left unconnected.
3