GP4020 Datasheet, PDF (2/17 Pages) Zarlink Semiconductor Inc – GPS Receiver Baseband Processor

GP4020
U2RXD
U2TXD
U1RXD
U1TXD
NICE
NTRST
WDOG
UART_CLK
UART2
DMAC
UART1
TIC
SSM
ARM7
TDMI
MICRO
JTAG
JTAG
INTERFACE
GPIO GPIO
BSIO BSIO
BµILD_CLK
NRESET
PERIPHERAL
CONTROL
LOGIC
FIREFLY
MF1 CORE
INTC
PER_INT
MEAS_INT
ACCUM_INT
REAL
TIME
CLOCK
RTC_CLK
UART_CLK
NPOR_RESET
UIM BUS
NRESET
PLL
SYSTEM
CLOCK
GENERATOR
M_CLK
12-CHANNEL
GPS
CORRELATOR
UIM
MPC
NPOR_
RESET
UIM BUS
1PPS
TIMEMARK
GENERATOR
BOOT
ROM
512316
SRAM
2K332
(6ns)
PLLAT1
PR_XIN
PR_XOUT
CLK_I
CLK_T
SAMPCLK
MAG0
SIGN0
RF_PLL_LOCK
IEXTINT2
TIMEMARK/TIC
GP4020
Figure 1 - Block diagram
2