YSS950 Datasheet, PDF (5/30 Pages) YAMAHA CORPORATION – DAP1 Digital Audio Processor

YSS950



























■ Comparison of Yamaha audio DSP


Chip Name
Function
Dolby digital decoding
Dolby Digital EX decoding
AAC decoding
PCM input playback
Dolby Pro Logic II decoding
Dolby Pro Logic IIx decoding
DAP1
YSS950
N
N
N
Y (up to 16 channelsʣ
Y
Y
ADAMB
YSS944 YSS943 YSS940


Y




Y




Y


Y (up to 8 channelsʣ


Y




Y


EVE
YSS920B
N
N
N
Y (up to 16 channels)
N
N
DTS decoding
N
Y
Y
N
N
DTS 96/24 decoding
DTS-ES decoding
DTS Neo:6 decoding
Tone control
Bass management
Volume adjustment
Noise generation
Impulse generation
Dynamic range controller
N
Y
Y
N
N
N
Y
N
N
N
N
Y
N
N
N
Y


Y


Y
Y


Y


Y
Y


Y


Y
Y


Y


Y
Y


Y


Y
Y


Y


Y
Harmonics regenerator
Nch surround
Sound field
Virtual surround
Headphone surround
Y
Y (Mixer)
Y
Y
Y
N


Y




Y




Y




Y


N
Y(Channel Distributor)
Y
Y
N
Parametric equalizer
Graphic equalizer
Channel divider
Automatic acoustic calibration
Down mixing
Mixer
Y (8ch x 8Band x X)
Y (PEQ implementation)
Y
Y
Y (Mixer)
Y
Y (8ch x 5Band)
Y (PEQ implementation)


Y




Y




Y




N


Y (5ch x 3Band)
Y(2ch x 10band)
Y
N
Y
Y
Down sampling
Y (16 channels)
Y (2 channels)
N
Modification of firmware placement
Y


N


N
Multiple firmware calls
User programmability
Precision of calculations
Microcontroller interface
Y


N


Y (design with module)


N


Internal data bus:32-bit floating point (24-bit mantissa, 8-bit exponent),
Coefficient : 32-bit floating point
Four-wire serial interface
N
Y(design with assembler)
Internal data bus:32-bit floating point
(28-bit mantissa, 4-bit exponent),
Coefficient : 16-bit fixed point
Firmware download
Y
Digital audio interface
24 bits (fixed) or 32 bits
(floating) × 16 channels,
TDM (4 channels or 8 channels)
is enabled
Audio data channel switching control
Y (input and output)
Bypass
Y
User mute
Y (input and output)


Y


24 bits (fixed) ×8 channels
Y (output)


Y


Y (output)
Y
24 bits (fixed) or 32 bits (floating) ×
16 channels
N
Y (realize by firmware)
Y (output)
External memory interface
Input delay (lip sync)
Output delay
Stream detection
Auto mute
Status port
General-purpose I/O ports
Internal operation clock generator
Power-up/power-down
N
Y
Y
N
Y
Auto mute, interrupt
4
Y
Y
SRAM (4Mbit)


Y




Y




Y




Y


Zero detection, auto mute, interrupt


8




Y




Y


DRAM or SRAM (4Mbit)
Y
Y
N
N
Zero detection, etc
20
Y
N
Operation frequency
165.888 MHz
178.176MHz
50MHz
Power supply voltage
Power consumption (Typ.)
1.2V (core), 3.3V (pin)
130 mW
211mW (Dolby Digital decoding)
2.5V (core), 3.3V (pin)
165mW
Package
Lead-free
SQFP64
Y
LQFP144


Y


SQFP100
Y
[Caution]
“Dolby”, “Dolby Pro Logic II”, and “Dolby Pro Logic IIx” are trademarks of Dolby Laboratories.
“DTS”, “DTS-ES”, “DTS-96/24”, and “DTS Neo:6” are trademarks of Digital Theater Systems, Inc.
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