YSS950 Datasheet, PDF (24/30 Pages) YAMAHA CORPORATION – DAP1 Digital Audio Processor

YSS950


































(b) Serial peripheral interface
Parameter
Symbol Conditions
Min.
Typ.
SCK cycle
SCK high level time
SCK low level time
/CS high level time
/CS and SI setup time
/CS and SI hold time
SO delay time
SO disable time
t_SCK
80
t_SCKH
40
t_SCKL
40
t_CSH
80
t_SIS
[Note 1]
10
t_SIH
[Note 1]
10
t_SOD
CL = 50 pF
t_SOZ
CL = 50 pF
[Note 1] Satisfy the setup time/hold time (vs. SCK) on starting or ending transfer, with /CS = L.
Max.
Unit
ns
ns
ns
ns
ns
ns
30
ns
20
ns
/CS
SCK
SI
SO
t_SIS
High-Z
t_SCK
t_SCKL
t_SCKH
t_SIS
t_SIH
t_SOD
t_CSH
t_SIH
t_SOZ




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