YSS950 Datasheet, PDF (16/30 Pages) YAMAHA CORPORATION – DAP1 Digital Audio Processor

YSS950




































(b) Interface format
1) Input format
The normal mode timing is illustrated below. 32-bit data can be input via the two channels from SDI0, SDI1,
SDI2, SDI3, SDI4, SDI5, SDI6, and SDI7. (n) indicates the current frame input sample and (n − 1) indicates
the previous frame input sample.
1 frame (1/fs = 64 SDIBCKs)
SDIWCK SDIWCKP=0
SDIWCKP=1
SDIBCK SDIBCKP=0
32 SDIBCKs
32 SDIBCKs
SDI*
SDIBCKP=1
SDITFMT=0b00
SDIBIT=0bxx
SDITFMT=0b10
SDIBIT=0bxx
SDITFMT=0b01
SDIBIT=0b00
SDITFMT=0b01
SDIBIT=0b01
SDITFMT=0b01
SDIBIT=0b10
SDITFMT=0b01
SDIBIT=0b11
SDI*L(n)
SDI*R(n)
M
S
B
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
LM
SS
BB
1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 14 12
L
S
B
10
SDI*L(n)
SDI*R(n)
M
S
B
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
L
S
B
2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13
L
S
B
210
SDI*R(n-1)
SDI*L(n)
SDI*R(n)
LM
SS
BB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28
LM
SS
BB
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28
17 16
SDI*R(n-1)
SDI*L(n)
SDI*R(n)
LM
SS
BB
13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26
LM
SS
BB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26
15 14
SDI*R(n-1)
SDI*L(n)
SDI*R(n)
LM
SS
BB
11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24
LM
SS
BB
13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24
13 12
SDI*R(n-1)
SDI*L(n)
SDI*R(n)
LM
SS
BB
7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20
LM
SS
BB
9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20
98


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