YSS950 Datasheet, PDF (13/30 Pages) YAMAHA CORPORATION – DAP1 Digital Audio Processor

YSS950



























2) Runtime transfer mode
During runtime transfer mode, coefficient data firmware can be downloaded. This mode enables the
coefficient to be changed without jitter, even during signal processing. The runtime processing mode’s
features are listed below.
• Transfers are performed while signal processing is continued. Auto mute is not set during the transfer
period.
• Up to 32 words of transfer data is buffered and written to on-chip memory as a batch.
• Downloading of coefficient data firmware is supported.
The runtime transfer mode’s steps for on-chip memory access are illustrated below.
(1)
/CS
16 SCKs
16 SCKs
16x3 SCKs
32 SCKs
32x(n-1) SCKs
SCK
SI
Write
RTCNT=0
Write
OMASUM=0
Write
OMAA=A,OMA=1
Write
D[0]
Write
D[1]
Write
D[n-1]
(RTCNT)
0
1
n-1
Don't care
Don't care
n
(OMA)
<1>
Setup (transfer to on-chip buffer)
• Initialize the transfer data count (RTCNT[5:0] = 0).
• Initialize the checksum as necessary. ʢOMASUM[7:0]=0ʣ
• Set the start address for on-chip memory (example: 0MAA[20:0] = A).
• Change the serial peripheral interface’s pin function from register access to on-chip memory access
(OMA = 1).
• The specified amount of data at consecutive addresses is transferred in 32-bit units, and in LSB first
sequence.
• The transfer data count (RTCNT[5:0]) is automatically incremented each time 32 bits of data are
written.
• Transfer of data to on-chip buffers ends when /CS = H is set.
(2)
(3)
/CS
16 SCKs
16 SCKs
16 SCKs
SCK
Don't care
Don't care
SI
Don't care
Write
RTREQ=1
SO
High-Z
Read
RTREQ
Read
RTREQ
Don't care
(RTCNT)
n
(OMAA)
A
(RTREQ)
<2>
Start (transfer from on-chip buffer to on-chip memory)
• Start of data transfer is requested (RTREQ = 1).
<3>
End
• End of data transfer is confirmed (RTREQ = 0, IRFW[0]=1).
• OMASUM[7:0] is notified of the checksum of the transferred data.
[Note]
• On-chip buffer transfer can be interrupted by setting /CS to high level. If a transfer is interrupted before
the rising edge of SCK in the 32nd data bit, the write operation is not performed.
• When transferring to non-consecutive addresses or when re-executing after the on-chip buffer transfer
has been interrupted, start from step (1) above.
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