YSS950 Datasheet, PDF (27/30 Pages) YAMAHA CORPORATION – DAP1 Digital Audio Processor

YSS950



























5) SDOBCK, SDOWCK, SDO7 to SDO0 (master operation)
Parameter
Symbol Conditions
Min.
Typ.
Max.
Unit
SDOBCK output frequency
f_SDOBCK
[Note 2]
12.5
MHz
SDOBCK duty factor
d_SDOBCK
[Note 1, 3]
50
%
SDOBCK rise time
t_SDOBCKR
CL = 50 pF
15
ns
SDOBCK fall time
t_SDOBCKF
CL = 50 pF
15
ns
SDOWCK, SDO7 to SDO0 delay time
t_SDOD
CL = 50 pF
−15
15
ns
SDIBCK → SDOBCK delay time
t_SDOBCKD
CL = 50 pF
[Note 4]
0

ns
[Note 1]
[Note 2]
[Note 3]
[Note 4]
The polarity of SDIBCK and SDOBCK can be changed by SDIBCKP and SDOBCKP. In the following figure,
SDIBCKP = SDOBCKP = 0.
Although output divided from SDIMCK can be selected for SDOBCK via SDOBCKS[2:0], operation is not
guaranteed if SDIMCK’s frequency exceeds the range noted above.
When SDIBCKS through has been selected by SDIBCKS[3:0] = SDOBCKS[3:0] = 0b0000, output is affected by
the SDIBCK duty factor.
When SDIBCKS through has been selected by SDIBCKS[3:0] = SDOBCKS[3:0] = 0b0000.
SDIBCK
SDOBCK
SDOWCK
SDO7 to SDO0
t_SDOBCKD
t_SDOBCKR
t_SDOBCKF
t_SDOD
t_SDOD
f_SDOBCK
d_SDOBCK
d_SDOBCK
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