YSS950 Datasheet, PDF (17/30 Pages) YAMAHA CORPORATION – DAP1 Digital Audio Processor

YSS950





























The TDM 4ch mode timing is illustrated below. 32-bit data can be input via the four channels from SDI0,
SDI2, SDI4, and SDI6.
The supported data format is the same as for normal mode.
1 frame (1/fs = 128 SDIBCKs)
SDIWCK SDIWCKP = 0
SDIWCKP = 1
SDIBCK SDIBCKP = 0
SDIBCKP = 1
32 SDIBCKs
32 SDIBCKs
32 SDIBCKs
32 SDIBCKs
SDI0
SDI0L(n)
SDI0R(n)
SDI1L(n)
SDI1R(n)
SDI2
SDI2L(n)
SDI2R(n)
SDI3L(n)
SDI3R(n)
SDI4
SDI4L(n)
SDI4R(n)
SDI5L(n)
SDI5R(n)
SDI6
SDI6L(n)
SDI6R(n)
SDI7L(n)
SDI7R(n)
The TDM 8ch mode timing is illustrated below. 32-bit data can be input via the eight channels from SDI0 and SDI4.
The supported data format is the same as for normal mode.
1 frame (1/fs = 256 SDIBCKs)
SDIWCK SDIWCKP = 0
SDIWCKP = 1
SDIBCK SDIBCKP = 0
SDIBCKP = 1
32 SDIBCKs 32 SDIBCKs 32 SDIBCKs 32 SDIBCKs 32 SDIBCKs 32 SDIBCKs 32 SDIBCKs 32 SDIBCKs
SDI0
SDI0L(n)
SDI0R(n)
SDI1L(n)
SDI1R(n)
SDI2L(n)
SDI2R(n)
SDI3L(n)
SDI3R(n)
SDI4
SDI4L(n)
SDI4R(n)
SDI5L(n)
SDI5R(n)
SDI6L(n)
SDI6R(n)
SDI7L(n)
SDI7R(n)


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