YSS950 Datasheet, PDF (11/30 Pages) YAMAHA CORPORATION – DAP1 Digital Audio Processor

YSS950



























■ FUNCTION DESCRIPTION
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Serial Peripheral Interface
This LSI provides a four-wire serial peripheral interface (SPI) for the /CS, SK, SI, and SO pins. The
microcontroller accesses the following via this serial peripheral interface
• Register address
• On-chip memory access (firmware download)
The following is a status transition diagram for the serial peripheral interface.
/CS=L
Register settings for
on-chip memory access
Device
not selected
Register access
/CS=H
/CS=H
On-chip
memory access
(Firmware download)
[Note]
In this manual, “register access” is the means of accessing on-chip memory, and should be considered as
functionally similar to “firmware download”.
(a) Register access
Register access is performed in 16-bit units via the serial peripheral interface. SI is used to specify the register
address (7 bits: A6 to A0) and the read/write setting (1 bit: R/W). During a write operation (R/W = L), data
(8 bits: D7 to D0) should be written to SI, and during a read operation (R/W = H), 8-bit data should be read
from SO. The write data is stored internally at the rising edge of SCK in the last data bit (D7 in the diagram).
The serial peripheral interface sequence during register access is illustrated below.
/CS
SCK
Don't care
Don't care
SI
Don't care A0 A1 A2 A3 A4 A5 A6 R/W D0 D1 D2 D3 D4 D5 D6 D7 Don't care
Write
SO
High-Z
operation
(R/W = L)
SI
Don't care A0 A1 A2 A3 A4 A5 A6 R/W
Don't care
Read
SO
High-Z
D0 D1 D2 D3 D4 D5 D6 D7 ^High-Z
operation
(R/W = H)
[Note]
• SO is in output mode only during data read operations when /CS = L. Otherwise, high impedance output
is set, so that SCK, SI, and SO can be shared with other devices that have a similar interface.
• Continuous register access is enabled when /CS = L. There is no need to set /CS = H between access
times.
• During a hardware reset (/RST = L), keep /CS to high level (/CS = H)..
• If /CS = H is set during register access, access is stopped. Any write operation that occurs prior to the
rising edge of the 16th SCK signal (SI’s D7 data capture clock) is invalid. SO is set to high impedance.
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