DS525 Datasheet, PDF (9/13 Pages) –

802.16e CTC Encoder v3.0
Output Control Signals
The RDY signal is driven High to indicate that there is valid data on the systematic and parity ports. The
BLK_START signal is driven High for one clock cycle at the start of an output block as shown in
Figure 6.
Figure Top x-ref 6
CLK
CE
SYST_A
D SYST_B
PAR_Y1
PAR_W1
is_{PAR_Y2}
PAR_W2
c_RDY
BLK_START
o _{BLK_END}
A0 A1 A2
A3
A4 A5
B0 B1 B2
Y1_0 Y1_1 Y1_2
B3
Y1_3
B4 B5
Y1_4 Y1_5
W1_0 W1_1 W1_2 W1_3 W1_4 W1_5
Y2_0 Y2_1 Y2_2 Y2_3 Y2_4 Y2_5
W2_0 W2_1 W2_2 W2_3
W2_4 W2_5
An-2 An-1 a0 a1 a2 a3
Bn-2 Bn-1 b0 b1 b2 b3
Y1_n-2 Y1_n-1 y1_0 y1_1 y1_2 y1_3
W1_n-2 W1_n-1 w1_0 w1_1 w1_2 w1_3
Y2_n-2 Y2_n-1 y2_0 y2_1 y2_2 y2_3
W2_n-2 W2_n-1 w2_0 w2_1 w2_2 w2_3
n _{Figure 6: Output Timing}
t _Latency
i _{The latency is defined as the number of cycles from when the first input data couple is sampled until}
n _{the first encoded output. In other words, the time from the FD_IN input being sampled until the}
BLK_START output being asserted for that block.
u _{Due to the triple-buffered architecture, all data must be written to RAM, read out first to the precoder,}
and then again to the main encoder. In the case where the block size is invariant, the latency is therefore
e ^{a few cycles more than twice the block size in couples.}
In general, when the block size is not constant, there may be an additional component to the latency,
d ^{such as a larger block already being processed. The worst case first-in-to-first-out latency for any given}
block is therefore just over twice the largest block size in couples. This can be understood by referring
to the previous section on triple-buffering. Some latency values for fixed block sizes are given in table
Table 2.
IP _{Table 2: Latency Values for Fixed Block Sizes}
Blk_size
Block Size N
(Couples)
Latency
First Input to First Output
(Typical)(Cycles)
6
24
58
9
36
82
12
48
106
18
72
154
24
96
202
DS525 April 24, 2009
www.xilinx.com
9
Product Specification