DS525 Datasheet, PDF (3/13 Pages) –

802.16e CTC Encoder v3.0
Table 1: I/O Ports, Basic Configuration (Continued)
Port
Pin
Sense Width
(bits)
Description
RDY
BLK_START
D_{BLK_END}
Output
Output
Output
1
Ready. The output is asserted (High) when there is valid data
on the systematic and parity outputs.
Block Start. The output is asserted (High) for one clock cycle
1
to signal the start of a valid block on the systematic and parity
outputs.
Block Start. The output is asserted (High) for one clock cycle
1
to signal the end of a valid block on the systematic and parity
outputs.
i_{Asynchronous Clear (ACLR)}
s_{The ACLR input port is optional. When ACLR is driven High, the core resets to its initial state and is}
ready to process a new block. Following the initial configuration of the FPGA, the core is automatically
c_{in the reset state, so no further ACLR is required before an encoding operation can take place. ACLR is}
the only asynchronous input to the core.
o _{Clock (CLK)}
With the exception of asynchronous clear, all operations of the core are synchronized to the rising edge
n _{of CLK. If the optional CE pin is enabled, an active rising clock edge occurs only when CE is High.}
Clock Enable (CE)
t _{Clock enable is an optional input pin that is used to enable the synchronous operation of the core.}
i _{When CE is High, a rising edge of CLK is acted upon by the core, but if CE is Low, the core remains in}
n _{its current state. An active, rising clock edge is one on which CE (if enabled) is sampled High.}
Synchronous Clear (SCLR)
u _{The SCLR signal is optional. When SCLR is sampled High on an active rising clock edge, the core is reset}
to its initial state and is ready to process a new block. Following the initial configuration of the FPGA,
e _{the core is automatically in the reset state; no further SCLR is required before an encoding operation can}
take place. If the CE input port is selected, the SCLR is ignored if CE is Low.
d _{Data Input Ports (DATA_IN_A / DATA_IN_B)}
The DATA_IN ports are mandatory input ports that carry the unencoded double-binary data couples.
The input process is started with a First Data (FD_IN) signal. When FD_IN is sampled High, the value
IP _{on the DATA_IN_A port is the MSB of the first byte of unencoded data. Data couples are read serially}
into the DATA_IN port on a clock-by-clock basis. BLK_SIZE*4 clock cycles are therefore required to
input each block.
First Data (FD_IN)
FD_IN is a mandatory input port, which is used to start the encoder operation. When FD_IN is sam-
pled High on an active rising clock edge, the first data couple is read from the DATA_IN_A and
DATA_IN_B ports, and the block size is read from the BLK_SIZE port. The core then continues loading
data until a complete block has been input.
The FD_IN input should only be asserted when the RFFD output is High (see below). If FD_IN is sam-
pled High when RFFD is Low, this is an abort condition, and the behavior of the core is not specified.
DS525 April 24, 2009
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Product Specification