DS525 Datasheet, PDF (11/13 Pages) –

802.16e CTC Encoder v3.0
Performance and Resource Usage
Some typical performance and resource usage figures for minimal and maximal implementations on
Virtex-5 parts are given in Table 3.
Table 3: Performance and Resource Usage
With CE, SCLR, and ACLR
Note
Virtex-5
XC5VSX95T-1
Area (LUT6-FF pairs)
1
741
Area (Registers)
1
609
D_{36K Block Memories}
1
2
18K Block Memories
1
3
i_{MULT18x18s or DSP48s}
1
0
s_{Speed (MHz)}
1,2,3
303
c_{Without CE, SCLR, or ACLR}
Note
Virtex-5
XC5VSX95T-1
o ^{Area (LUT6-FF pairs)}
1
666
Area (Registers)
1
608
n 36K Block Memories
1
2
18K Block Memories
1
3
t _{MULT18x18s or DSP48s}
1
0
i _{Speed (MHz)}
1,2,3
303
n _Notes:
1. Area and maximum clock frequencies are provided as a guide. They may vary with new releases of Xilinx implementation
tools, etc.
u 2. Obtained with the core instantiated within a double registered wrapper, and with the outer wrapper registers in the IOBs. Area
figures do not include the inner wrapper registers.
3. Clock frequency does not take clock jitter into account and should be derated by an amount appropriate to the clock source
jitter specification.
e _Throughput
d _{The throughput is greatest when larger block sizes are used. Table 4 shows the throughput values}
obtained for some typical block sizes.
Table 4: Throughput Values
IP _{Block Size}
Input Data Throughput
(Couples)
(% of Clock Frequency)
24
94.7
216
99.4
480
99.7
2400
99.9
DS525 April 24, 2009
www.xilinx.com
11
Product Specification