DS525 Datasheet, PDF (8/13 Pages) –

802.16e CTC Encoder v3.0
Input Control Signals
Figure 5 shows the signals associated with the data input side of the core.
When FD_IN is sampled High on an active rising edge of CLK, the RFFD signal is driven Low to indi-
cate that the core is no longer waiting for FD_IN. The block size (in bytes), in this case n/4, of the current
input block is sampled on the BLK_SIZE port, and the first data couple, A0 and B0, is sampled on the
DATA_IN ports.
The core continues to input data until n new data couples have been accepted, and then the core stops
sampling the DATA_IN ports.
D_{When the core is ready to accept a new block of data, RFFD is driven High.}
After asserting RFFD, the core waits until the next FD_IN pulse, and then a new write cycle is started,
i^{in this case with block size m/4.}
Figure Top x-ref 5
scCLK
CE
o _RFFD
FD
n _{BLK_SIZE}
DATA_IN_A
t _{DATA_IN_B}
n/4
A0 A1 A2 A3
B0 B1 B2 B3
A4 A5
B4 B5
m/4
An-2 An-1 a0 a1 a2 a3
Bn-2 Bn-1 b0 b1 b2 b3
inued _{IP Figure 5: Input Timing}
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DS525 April 24, 2009
Product Specification