DS525 Datasheet, PDF (2/13 Pages) –

802.16e CTC Encoder v3.0
Two constituent encoders perform C1 (uninterleaved) and C2 (interleaved) encoding. Two other con-
volutional encoders are employed as precoders that calculate the circulation states for the two main
encoders. The constituent encoders are described later in this data sheet.
A triple-buffered rotating memory bank permits C1 and C2 encoding, and the calculation of the circu-
lation states all to be performed simultaneously for maximum data throughput.
The encoder block size can be changed on a block-by-block basis, using the BLK_SIZE input port. All
block sizes specified by the 802.16e standard, ranging from 6 to 600 bytes are supported.
Flexible handshaking is facilitated by the FD_IN input port and the output ports RDY, BLK_START,
DBLK_END, and RFFD.
The fundamental specification of the encoder, including block sizes, determination of the circulation
states, and the interleaver specification can be found in the IEEE 802.16e standard[1].
is_{Input/Output Ports}
The I/O ports for the basic configuration are summarized in Table 1 and described below.
c_{Table 1: I/O Ports, Basic Configuration}
Port
o_Pin
Sense Width
(bits)
Description
n _{FD_IN}
Input
1
First Data. When sampled High on an active rising clock
edge, the encoding process is started.
t _ACLR
Input
(optional)
1
Asynchronous Clear. When this is asserted (High), the
encoder asynchronously resets.
in _SCLR
Input
(optional)
1
Synchronous Clear. When sampled High on an active rising
clock edge, the encoder is reset.
u _CE
Input
(optional)
1
Clock Enable. When Low, rising clock edges are ignored and
the core is held in its current state.
e CLK
Input
1
Clock. All synchronous operations occur on the rising edge of
the clock signal.
d ^BLK_SIZE
Input
10
Block Size. Sets up the block size (in bytes) when First Data
(FD_IN) is sampled high. Ignored if FD_IN is Low.
DATA_IN_A
Input
1
Data Input A. The A-channel of the data to be encoded.
DATA_IN_B
Input
1
Data Input B. The B-channel of the data to be encoded.
IP _{SYST_A}
Output
1
RSC1 Systematic A.The systematic A output from RSC1.
SYST_B
Output
1
RSC1 Systematic B. The systematic B output from RSC1.
PAR_Y1
Output
1
RSC1 Parity Y. The Y parity output from RSC1.
PAR_W1
Output
1
RSC1 Parity W. The W parity output from RSC1.
PAR_Y2
Output
1
RSC2 Parity Y. The Y parity output from RSC2.
PAR_W2
Output
1
RSC2 Parity W. The W parity output from RSC2.
RFFD
Output
1
Ready for First Data. When the output asserted (High), the
core is ready to start another encoder operation.
2
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DS525 April 24, 2009
Product Specification