DS525 Datasheet, PDF (1/13 Pages) –

802.16e CTC Encoder v3.0
DS525 April 24, 2009
Product Specification
Features
Applications
• Drop-in module for Spartan®-6, Spartan-3E,
Spartan-3A/3AN/3A DSP, Spartan-3, Virtex®-6,
Virtex-5 and Virtex-4 FPGAs
D• Implements the IEEE 802.16e Wireless MAN
OFDMA PHY CTC encoder specification [1]
• Supports optional 64-QAM modulation
i• Supports optional hybrid-ARQ (HARQ)
s _{• Multiplexed symbol memory for maximum}
throughput
c _{• Simultaneous C1 and C2 encoding}
• Pipelined data paths for speed
o _{• Flexible interfacing by means of optional control}
signals
n _{• Designed for minimum area and maximum speed}
• Available using the CORE Generator™ software
t _{v11.1, which is included with the ISE™ v11.1 tools}
The Convolutional Turbo Code (CTC) encoder meets
the Wireless MAN OFDMA PHY CTC encoder specifi-
cation of the IEEE 802.16e standard [1] and supports the
optional hybrid ARQ (HARQ).
General Description
The theory of operation of the Turbo Codes is described
in the paper by Berrou, Glavieux, and Thitimajshima
[2].
The CTC Encoder core is a parallelized implementation
of the convolutional turbo coder specified by the IEEE
802.16e Wireless MAN OFDMA PHY CTC encoder
specification [1].
The input and output ports of the CTC encoder core are
shown in Figure 1.
inue _{Figure Top x-ref 1}
Mandatory Pins
CLK
FD_IN
DATA_IN_A
DATA_IN_B
10
BLK_SIZE
d _{IP Optional pins}
SYST_A
SYST_B
PAR_Y1
PAR_W1
PAR_Y2
PAR_W2
RDY
BLK_START
BLK_END
RFFD
Multi-bit
Single-bit
ACLR
SCLR
CE
Figure 1: Pinout
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DS525 April 24, 2009
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Product Specification