DS525 Datasheet, PDF (6/13 Pages) –

802.16e CTC Encoder v3.0
Internal Architecture
The internal architecture of the core is shown in Figure 3.
Figure Top x-ref 3
BLK_SIZE
FD_IN
M1_DOUTA
Double-binary
data couple
DATA_IN(A:B)
DINA
D ^M1 _DINA
isc _{M2 DINA}
o_{M3 n Memory Bank}
M1_DOUTA
M1_DOUTB
M2_DOUTA
M3_DOUTA
M1_DOUTB
M2_DOUTB
M3_DOUTB
PRECODER 1
CS1
PRECODER 2
Interleaver
(Precoder)
CS2
ADDRESS x 6
CONTROL x 6
M2_DOUTA
M2_DOUTB
MEMORY
CONTROL
M3_DOUTA
M3_DOUTB
M1_DOUTB
M2_DOUTB
M3_DOUTB
M1_DOUTA
M2_DOUTA
M3_DOUTA
TIMING
CONTROL
Interleaver (Main)
ENCODER RSC2
ENCODER RSC1
RDY
BLK_START
RFFD
PAR_Y2
PAR_W2
PAR_Y1
PAR_W1
SYST_A
SYST_B
tin_{Figure 3: CTC Encoder Structure}
The sequence of input data couples is written into one of three dual-port memory buffers, while data
u _{from the other two dual-port memories are streamed out to the precoders and the encoders. The three}
dual-port memories are rotated every block.
e _{Data couples read out of the DOUTA ports of the memory bank are in uninterleaved (natural) order,}
whereas those read from the DOUTB ports are in interleaved order.
d _{Triple-buffering for Maximum Throughput}
As described previously, the encoder employs six parallel outputs, and a triple-buffered memory archi-
tecture for maximum throughput. Figure 4 illustrates the utilization of the three memories, M1, M2,
IP _{and M3, and the effects on throughput of changing the block size.}
The throughput is at a maximum if the block size is constant, as in Figure 4(a). In this case, the output
data is continuous, with the exception that due to internal delays there is a 4-cycle gap every third
block. This is signalled on the output side by a Low on RDY and on the input side by a delay in RFFD of
five cycles once every third block.
Figure 4(b) shows the effect of increasing the block size. Since it takes longer to write a large block into
memory than it does to read a smaller one out, the memory controller needs to wait for the larger block
to be written before it can rotate the buffers. This causes a gap in the output data, which is signalled by
a Low on RDY.
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DS525 April 24, 2009
Product Specification