DS449 Datasheet, PDF (9/9 Pages) Xilinx, Inc – LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2.11f)

LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2.11f)
Date
11/11/05
07/12/06
02/11/06
05/23/07
6/25/07
6/24/09
4/19/10
3/1/11
6/22/11
10/19/11
12/18/12
Version
1.5
1.6.1
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
Revision
In Allowable Parameters Combinations: In C_FSL_DEPTH: C_ASYNC_CLKS is set to 0, was
C_SYNC_CLKS is set to 1; In C_IMPL_STYLE, last sentence was: This parameter affects timing:
When the FiFO is empty, there is a one cycle delay before FSL_S_Exists goes high.
Minor correction on page 7; Incorporated CR232700
CR419924; Asynchronous mode together with BRAM implementation of FIFO now supported;
CR415462 and CR304088, For Asynchronous mode, C_ASYNC_CLKS=1, FIFO_DEPTH < 16 is
not allowed; added Spartan-3A and Virtex-5 FPGAs to supported device listing; FSL_Control_IRQ
signal: added FSL_Control_IRQ, FSL_Has_Data and FSL_Full possible to automatically connect
to interrupt controller; CR426522: Write Operation when FULL Flag asserted; CR426524: Reset
Descriptions section added
CR432809: Ambiguity in what happens for FSL_S_Read when FSL_S_EXISTS is low and for
FSL_M_WRITE when FSL_S_FULL is high; CR432811: Allowable values for C_FSL_WIDTH;
CR432812: FSL_Full is specified as an input instead of output; CR433775: Async FSL pcore is
causing timing violations between FSL pcore and the Microblaze processor; CR438690: FSL
v2.10.a cannot handle back to back read, fixed; CR439091: FSL v2.10.a assigns exists flag too
early, fixed; MicroBlaze Soft Processor FSL Interface section updated; supported Target
Technology updated
Changed FSL_S_EXISTS signal direction in Figure 1; updated legal footer.
Updated for 11.2.
Created version 2.11c for 12.1 release; incorporated CR513242 by adding C_FSL_DEPTH in the
range 2-15 which results in a FIFO depth of 16 when C_ASYNC_CLKS=0 as table note 1 in Table
2; incorporated CR524441 with minor edits.
Created version 2.11d for 13.1 release; clearified C_FSL_DEPTH values for different
configurations, added table note 2 and 3 in Table 2
Fixed pointer issue for large synchronous FIFOs
Added explanation of why "ENABLE=sr_reg_o" needs to be added for asynchronous FIFO using
LUTRAM
Updated notice of disclaimer
Xilinx tools support for 13.3 release
Updated for 14.4.
• Fixed issue with sync FIFO BRAMs which could duplicate read data.
• Fixed issue with incorrect control bit propagation when C_FSL_DEPTH is 1.
• Corrected Reset Descriptions.
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DS449 December 18, 2012
www.xilinx.com
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Product Specification