DS449 Datasheet, PDF (4/9 Pages) Xilinx, Inc – LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2.11f)

LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2.11f)
Parameter Descriptions
C_FSL_DEPTH
Specifies the depth of the FIFO implemented by the FSL bus. The depth can be as low as 1 or as high as 8192. The
depth specified is dependent on the implementation scheme of the FIFO. When the parameter C_ASYNC_CLKS is
set to 0, the depth allowed is between 1 and 8192 (2–15 results in a FIFO depth of 16). When the parameter
C_ASYNC_CLKS is set to 1 and C_IMPL_STYLE is set to 0 (LUT RAM), the depth allowed is between 16 and 128.
When the parameter C_ASYNC_CLKS is set to 1 and C_IMPL_STYLE is set to 1 (block RAM), the depth allowed is
between 512–8192. The depth must be 2ⁿ when C_ASYNC_CLKS is set to 1, but can have any allowed value when
C_ASYNC_CLKS is set to 0.
C_USE_CONTROL
This parameter specifies whether the control bit is propagated along with the data bit. When set to 1, the control bit
is transmitted from the master to the slave interface. When set to 0, the control bit transmitted to the slave is 0. When
propagation of control bit is not required, setting this bit to 0 enables reduction in the area of the FSL bus.
C_ASYNC_CLKS
This parameter specifies whether the FIFO in the FSL bus is implemented as a synchronous or asynchronous FIFO.
When set to 1, the FSL implements an asynchronous FIFO. In this case, the clock ports FSL_M_Clk and FSL_S_Clk
are used as the master and slave clocks, respectively. If set to 0, the FSL is implemented as a synchronous FIFO. In
this case, the clock port FSL_Clk is used for both the master and slave interfaces.
C_IMPL_STYLE
This parameter specifies the style of implementation of the FIFO of the FSL. If set to 1, the FIFO is implemented
using block RAMs. If set to 0, the FIFO is implemented using LUT RAMs.
Note: This parameter affects timing. When C_IMPL_STYLE=1, there is a one-cycle fall-through latency from a write to an
empty FIFO before FSL_S_Exists goes High.
If C_IMPL_STYLE = 0 and C_ASYNC_CLKS = 1 (using asynchronous LUT RAM FIFO), implementation tools do
not normally include the asynchronous set and reset path through flip-flops (DFFs). This can result in under-
constrained designs when using high clock frequencies. To ensure that the tools include these paths in the timing
analysis, the constraint “ENABLE=sr_reg_o;” must be added to the top-level constraints file (UCF). This
constraint includes an all asynchronous path using asynchronous set/reset to DFFs for the whole design. However,
this could create false critical paths for other parts of the design that need to be handled.
C_READ_CLOCK_PERIOD
When the parameter, C_ASYNC_CLKS is set to 1 and C_IMP_STYLE is set to 0, the parameter
C_READ_CLOCK_PERIOD must also be set. This parameter defines the period of FSL_S_CLK and is used for
generating timing constraints for the asynchronous path through LUT RAMs.
DS449 December 18, 2012
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