DS449 Datasheet, PDF (6/9 Pages) Xilinx, Inc – LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2.11f)

LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2.11f)
X-Ref Target - Figure 3
CLK
FSL_S_EXISTS
FSL_S_DATA
Data 1
Data 2
Data 3
FSL_S_CONTROL
Control 1
Control 2
Control 3
FSL_S_READ
Read 1
Figure 3: FSL Read Operation
Read 2
Read 3
DS449_03_062507
Write Operation
The write to the FSL bus is controlled by the FSL_M_Write signal. The following sequence of operations indicate
a write operation on the FSL bus. When the data in FSL_M_Data and control bit in FSL_M_Control are ready to
be pushed into the FIFO, the FSL_M_Write signal is set to 1 for one clock cycle. This pushes the data and control
signals into the FIFO. If the FIFO is not implemented with block RAMs, the data becomes available to the slave FSL
interface as FSL_S_Data and the control becomes available as FSL_S_Control after the write clock edge. There
is a one-cycle delay if using block RAMs when the FIFO length is zero. Further, the FSL_S_Exists signal is set to
1 to indicate that data exists in the FIFO.
The timing diagram in Figure 2 shows four write operations on the FSL bus. At the first clock edge the master
checks the FSL_M_Full signal and sees that it is not set. This allows the master to set the FSL_M_Write signal and
put the FSL_M_Data and FSL_M_Control on the bus. At the next clock edge, the data is read by the bus and
transferred into the FIFO. Writes 2 and 3 show back-to-back write operations. At write 3 the FIFO is full, which sets
FSL_M_Full. This forces the master to drop FSL_M_Write. After a read takes place, FSL_M_Full goes Low and
the master can issue another write. A read also takes place at write 4; otherwise, the FSL_M_Full would have gone
High again.
The FSL_M_Write is not gated with FSL_M_Full; the state of the FIFO is undefined when writing to a full FIFO.
Read Operation
The read side of the FSL bus is controlled by the FSL_S_Read signal. The following sequence indicates a read
operation on the FSL bus. When data is available in the FSL bus (FSL_S_Exists = 1), the data in FSL_S_Data and the
control bit in FSL_S_Control is immediately available to be read by the slave on the FSL bus. After the slave
completes the read operation, FSL_S_Read has to be set to 1 for one clock cycle acknowledging that a read has
successfully been completed by the slave. After the clock edge where the read takes place, the FSL_S_Data and
FSL_S_Control are updated with new data, and FSL_S_Exists and FSL_M_Full are updated. Figure 3 shows
the timing diagram for three read operations from the slave side of the FSL bus. Two writes take place between read
1 and read 2.
The FSL_S_Read is not gated with FSL_S_Exists; data read is undefined when reading an empty FIFO.
DS449 December 18, 2012
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Product Specification