DS449 Datasheet, PDF (5/9 Pages) Xilinx, Inc – LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2.11f)

LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2.11f)
Parameter - Port Dependencies
When the parameter C_ASYNC_CLKS is set to 0, the asynchronous write and read clock ports, FSL_M_Clk and
FSL_S_Clk, are not used in the design. The synchronous clock FSL_Clk is used as the clock port. When
C_ASYNC_CLKS is 1, the synchronous clock port, FSL_Clk is not used. The asynchronous read and write clock
ports, FSL_S_Clk and FSL_M_Clk, are used.
Reset Descriptions
After FPGA configuration, the FSL_V20 logic stays in a reset state for an additional 17 clock cycles.
After the external reset (SYS_Rst) has been deasserted, the FSL_V20 logic stays in a reset state for an additional
clock cycles. Exit of the reset state coincides with the deassertion of the FSL_Rst output signal.
Register Descriptions
Not applicable.
Interrupt Descriptions
The signals FSL_Has_Data, FSL_Full and FSL_Control_IRQ have interrupt properties such as, when asserted
an interrupt is generated, that facilitate connection to an interrupt controller.
Bus Operation
X-Ref Target - Figure 2
CLK
FSL_M_FULL
FSL_M_WRITE
FSL_M_DATA
Data 1
Data 2
Data 3
Data 4
FSL_M_CONTROL
Control 1
Write 1
Control 2 Control 3
Write 2 Write 3
Figure 2: FSL Write Operation
Control 4
Write 4
DS449_02_062507
DS449 December 18, 2012
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Product Specification