DS449 Datasheet, PDF (2/9 Pages) Xilinx, Inc – LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2.11f)

LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2.11f)
Functional Description
The Fast Simplex Link (FSL) V20 Bus is shown in Figure 1.
X-Ref Target - Figure 1
FSL_M_Clk
FSL_S_Clk
FSL_M_Data
FSL_M_Control
FSL_M_Write
FIFO
...
FSL_S_Data
FSL_S_Control
FSL_S_Read
FSL_M_Full
FSL_S_Exists
DS449_01_062507
Figure 1: FSL V20 Bus Block Diagram
FSL V20 Bus Core I/O Signals
The I/O signals and their function for the FSL V20 core are provided in Table 1.
Table 1: FSL_V20 I/O Signals
Signal Name
MSB:LSB
FSL_Clk
SYS_Rst
FSL_Rst
FSL_M_Clk
FSL_M_Data
FSL_M_Control
0:C_FSL_DWIDTH-1
FSL_M_Write
FSL_M_Full
FSL_S_Clk
FSL_S_Data
0:C_FSL_DWIDTH-1
I/O
Description
Input clock to the FSL bus when used in the synchronous FIFO mode
I (C_ASYNC_CLKS = 0). The FSL_Clk is used as the clock for both the
master and slave interfaces
I External system reset
Output reset signal generated by the FSL reset logic. Any peripherals
O connected to the FSL bus can use this reset signal to operate the
peripheral reset.
Port that provides the input clock to the master interface of the FSL
I
bus when used in the asynchronous FIFO mode (C_ASYNC_CLKS =
1). All transactions on the master interface use this clock when
implemented in the asynchronous mode
I Data input to the master interface of the FSL bus
Single bit control signal that is propagated along with the data at every
I
clock edge. Transmission of the control bit occurs when
C_USE_CONTROL is set to 1 (default). If the control bit is not used
by the slave, C_USE_CONTROL can be set to 0 to save area
Input signal that controls the write enable signal of the master
interface of the FIFO. When set to 1, the values of FSL_M_Data and
I
FSL_M_Control (if C_USE_CONTROL = 1) are pushed into the FIFO
on a rising clock edge. Note FSL_M_Write is not gated with
FSL_M_Full. The state of the FIFO is undefined when writing to a full
FIFO.
Output signal on the master interface of the FIFO indicating that the
O
FIFO is full. This signal can be used for hand-shaking and
synchronization between the master and slave connected through an
FSL bus
Port that provides the input clock to the slave interface on the FSL bus
I
when used in the asynchronous FIFO mode (C_ASYNC_CLKS = 1).
All transactions on the slave interface use this clock when
implemented in the asynchronous mode
O Data output bus onto the slave interface of the FSL bus
DS449 December 18, 2012
www.xilinx.com
2
Product Specification