DS449 Datasheet, PDF (1/9 Pages) Xilinx, Inc – LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2.11f)

DS449 December 18, 2012
LogiCORE IP Fast Simplex
Link (FSL) V20 Bus (v2.11f)
Product Specification
Introduction
The LogiCORE™ IP FSL V20 Fast Simplex Link (FSL)
Bus is a uni-directional point-to-point communication
channel bus used to perform fast communication
between any two design elements on the FPGA when
implementing an interface to the FSL bus. The FSL
interface is available on the Xilinx MicroBlaze^™
processor. The interfaces are used to transfer data to
and from the register file on the processor to hardware
running on the FPGA.
Features
• Implements a uni-directional point to point FIFO-
based communication
• Provides a mechanism for unshared and non-
arbitrated communication. This can be used for
fast transfer of data words between a master and a
slave, thus implementing the FSL interface.
• Provides an extra control bit for annotating
transmit data. This bit can be used by the slave-
side interface for different purposes, such as
decoding the transmit word as a control word, or
using the bit to indicate the start or end of frame
transmission.
• FIFO depths can be as low as 1K and as high as 8K.
• Supports synchronous and asynchronous FIFO
modes. This allows the master and slave side of the
FSL to clock at different rates.
• Support for SRL16 and dual port LUT RAM or
block RAM based FIFO implementation.
LogiCORE IP Facts
Supported Device
Family⁽¹⁾
Core Specifics
Virtex^®-6, Virtex-5, Virtex-4,
Spartan®-6, Spartan-3, Spartan-3E,
Spartan-3A/3A DSP/3AN,
Automotive Spartan-3/3A/3A DSP/ 3E
Resource Used
Min
Max⁽²⁾
Slices
21
451
LUTs
3
362
FFs
36
34
Block RAMs
0
17
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
N/A
Verification
N/A
Instantiation Template
N/A
Additional Items
N/A
Tested Design Tools⁽³⁾
Design Entry
ISE® 14.4
Verification
N/A
Simulation
Mentor Graphics ModelSim
Synthesis
XST
Support
Provided by Xilinx @ www.xilinx.com/support
1. For a complete listing of supported devices, see the release
notes for this core.
2. Maximum size in slices of FFs and LUTs is obtained using
parameter options, C_ASYNC_CLKS=1, C_FSL_DEPTH=128,
and C_USE_CONTROL=1. Maximum block RAM size is
obtained for parameter options C_ASYNC_CLKS=1,
C_FSL_DWIDTH=32, C_FSL_DEPTH=3182, and
C_USE_CONTROL=1.
3. For the supported versions of the tools, see the ISE Design
Suite 14: Release Notes Guide.
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are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
DS449 December 18, 2012
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Product Specification